本論文中，我們提出一個具有雙嵌入式氧化物負型金氧半負載的高集積密度非傳統單載子互補金氧半(Unipolar CMOS)。互補金氧半使用的兩顆金氧半場效電晶體皆為N型，傳輸載子為電子，故稱單載子互補金氧半。其中Q1 (driver)為傳統N型金氧半場效電晶體，Q2 (load)為雙嵌入式氧化物N型金氧半場效電晶體。利用雙嵌入式氧化物隔絕反轉層電流達到由貫穿電流主導目的，由於貫穿效應機制乃是非破壞性機制，因此不會對元件造成損壞。另外，因Q1與Q2皆為N型金氧半場效電晶體，故不必因載子移動率不同而在寬度有所補償，並且可因共享輸出電極且免除N-well製程步驟。因此規劃佈置圖時，相較於傳統互補金氧半反向器可節省72%面積，節省成本進而又可提高電晶體集積密度，且在延遲時間比傳統架構改進了39%，可大大提高操作頻率。

In this thesis, we propose a high density non-classical unipolar CMOS width two embedded oxide (2EO) NMOS load. The words “unipolar CMOS” refer to the fact that the conventional NMOS driver and the proposed 2EO NMOS load are presented in which the electron is the only carrier used. Among them, the 2EO scheme is used to isolate the inversion current. And the dominant current in the 2EO NMOS load is the punch through current which is not a destructive current mechanism. Our proposed CMOS, due to the same carrier used, does not have to compensate the layout width in load design. In addition, the shared terminal of output contacts and the elimination of N-well technique are also presented in our proposed CMOS. Therefore, the layout area can be reduced 72%, in comparison with conventional CMOS. Furthermore, the packing density can be increased and the fabrication cost can be reduced, respectively. We also find out that the delay time can be improved 39% to increase the operating frequency, as compared with the convention CMOS.

第一章 1
1.1背景 1
1.2動機 3
第二章 5
2.1 物理機制 5
2.1.1貫穿效應(Punch through effect) 5
2.2.2 空乏區寬度計算 6
2.2.3閘極控制空乏區寬度 7
2.2.4 平帶電壓(Flat-Band Voltage) 9
2.2.5 功函數差(Work Function ) 9
2.2.6 臨界電壓(Threshold Voltage) 9
2.3 傳統互補金氧半反向器操作原理 10
2.3.1 負載線 11
2.3.2 電壓轉換曲線 12
2.4 雙嵌入式氧化物之非傳統單載子電子傳輸互補金氧半操作原理 14
2.4.1負載線 16
2.4.2電壓轉換曲線 19
第三章 元件製程設計 21
第四章 模擬結果與物理模組 23
4.1 元件模擬所使用之物理模組 23
4.2 模擬結果與討論 24
4.2.1具有雙嵌入式氧化物負型金氧半負載的高集積密度非傳統單載子互補金氧半 24
4.3具雙嵌入式氧化物電晶體為負載之單載子互補金氧半與傳統互補金氧半佈局比較 36
4.4 數位邏輯電路之應用 37
4.4.1 反或閘(NOR) 37
4.4.2 反及閘(NAND) 39
4.4.3 環型振盪器(Ring oscillator) 41
4.4.4 全加器(Full adder) 42
4.4.5 靜態隨機存取記憶體(Static Random Access Memory) 44
4.4.6 2對2解碼器(2 to 2 Decoder) 46
4.5傳遞延遲時間(Propagation delay time) 47
第五章 結論與未來展望 51
參考文獻 52
附錄 56

[1] J. S. Kilby, “Invention of the Integrated Circuit,” IEEE Trans. Electron Device, ED-23, no. 7, pp.648-654, Jul. 1976.
[2] R. N. Noyce, “Semiconductor Device-and-Lead Structure,”IEEE Solid-State Circuits Newsletter, vol. 12, no. 2, pp.34-40, 2007
[3] F. M. Waelass and C. T. Sah, “Nanowatt Logic Using Field-Effect Metal-Oxide Semiconductor Triodes,” in Proc. IEEE Int. SSC Conf., pp.32-33, 1963.
[4] A. S. Sedra, and K. C. Smith, microelectronic circuits. 4th ed. New York: Oxford University Press, 1998.
[5] G. E. Moore, “Cramming more components onto integrated circuits,” Electronics, vol. 38, no. 8, 1965.
[6] S. M. Sze, Semiconductor Devices, Physics and Technology. 2nd ed. New York: John Wiley & Sons, 2001.
[7] M. Im, J.-W. Han, H. Lee, L.-E. Yu, S. Kim, C.-H. Kim, S. C. Jeon, K. H. Kim, G. Lee, J. S. Oh, Y. C. Park, H. M. Lee, and Y.-K. Choi, “Multiple-Gate CMOS Thin-Film Transistor With Polysilicon Nanowire,” IEEE Electron Device Lett., vol. 29, no. 1, pp.102-105, Jan. 2008.
[8] E. J. Tan, K. L. Pey, N. Singh, G. Q. Lo, D. Z. Chi, Y. K. Chin, L. J. Tang, P. S. Lee, and C. K. F. Ho, “Nickel-Silicided Schottky Junction CMOS Transistors With Gate-All-Around Nanowire Channels,” IEEE Electron Device Lett., vol. 29, no. 8, pp.902-905, Aug. 2008.
[9] S. Maheshwaram, S. K. Manhas, G. Kaushal, B. Anand, and N. Singh, “Vertical Silicon Nanowire Gate-All-Around Field Effect Transistor Based Nanoscale CMOS,” IEEE Electron Device Lett., vol. 32, no. 8, pp.1011-1013, Aug. 2011.
[10] X. Wu, C. H. Chan, S. Zhang, C. Feng, and M. Chan, “Stacked 3-D Fin-CMOS Technology,” IEEE Electron Device Lett., vol. 26, no. 6, pp.416-418, Jun. 2005.
[11] T.-J. King, “FinFETs for Nanoscale CMOS Digital Integrated Circuits,” in Proc. IEEE Int ICCAD Conf., 2005, pp.207-210.
[12] 林鴻志, “奈米金氧半電晶體元件技術發展驅勢(II),” 國家奈米實驗室-奈米通訊期刊, 第七卷, 第二期.
[13] R. Chau, S. Datta, M. Doczy, B. Doyle, J. Kavalieros, and M. Metz ,“High-K/Metal–Gate Stack and Its MOSFET Characteristics,” IEEE Electron Device Lett., vol. 25, no. 6, Jun. 2004.
[14] J. P. Colinge, Silicon-on-Insulator Technology: Material to VLSI. Amsterdam, The Netherland: Kluwer, 1991.
[15] E. Sangiorgi, B. Ricco, L. Selmi, “Three-dimensional distribution of CMOS latch-up current,” IEEE Electron Device Lett., vol. 8, no. 4, Apr. 1987.
[16] 林宏年, 呂嘉裕, 林鴻志, 黃調元, “局部與全面形變矽通道(strained Si channel)互補式金氧半(CMOS) 之材料、製程與元件特性分析(I),” 國家奈米實驗室-奈米通訊期刊, 第12卷, 第一期, pp.44-49.
[17] K.-W. Ang, K.-J. Chui, A. Madan, L.-Y. Wong, C.-H. Tung, N. Balasubramanian, M.-F. Li, G. S. Samudra, and Y.-C. Yeo, “Strained Thin-Body p-MOSFET With Condensed Silicon-Germanium Source/Drain for Enhanced Drive Current Performance,” IEEE Electron Device Lett., vol. 28, no. 6, pp. 509-512, Jun. 2007.
[18] S. Baudot, F. Andrieu, O. Weber, P. Perreau, J. F. Damlencourt, S. Barnola, T. Salvetat, L. Tosti, L. Brévard, D. Lafond, J. Eymery, and O. Faynot, “Fully Depleted Strained Silicon-on-Insulator p-MOSFETs With Recessed and Embedded Silicon–Germanium Source/Drain,” IEEE Electron Device Lett., vol. 31, no. 10, pp.1074-1076, Oct. 2010.
[19] W. W. Fang, N. Singh, L. K. Bera, H. S. Nguyen, S. C. Rustagi, G. Q. Lo, N. Balasubramanian, and D.-L. Kwong, “Vertically Stacked SiGe Nanowire Array Channel CMOS Transistors,” IEEE Electron Device Lett., vol. 28, no. 3, pp.211-213, Mar. 2007.
[20] M. Miyamoto, N. Sugii, Y. Hoshino, Y. Yoshida, M. Kondo, Y. Kimura, and K. Ohnishi, “Thick-Strained-Si/SiGe CMOS Technology With Selective-Epitaxial-Si Shallow-Trench Isolation,” IEEE Trans. Electron Device, vol. 54, no. 9, Sep. 2007.
[21] T.-Y. Liow, K.-M. Tan, R. T. P. Lee, C.-H. Tung, G. S. Samudra, N. Balasubramanian, and Y.-C. Yeo, “N-Channel (110)-Sidewall Strained FinFETs With Silicon–Carbon Source and Drain Stressors and Tensile Capping Layer,” IEEE Electron Device Lett., vol. 28, no. 11, pp.1014-1017, Nov. 2007.
[22] C.-T. Lin, Y.-K. Fang, W.-K. Yeh, C.-M. Lai, C.-H. Hsu, L.-W. Cheng, and G. H. Ma, “Impacts of Notched-Gate Structure on Contact Etch Stop Layer (CESL) Stressed 90-nm nMOSFET,” IEEE Electron Device Lett., vol. 28, no. 5, May. 2007.
[23] A.V-Y. Thean, D. Zhang, V. Vartanian, V. Adams, J. Conner, M. Canonico, H. Desjardin, P. Grudowski, B. Gu, Z.-H. Shi, S. Murphy, G. Spencer, S. Filipiak, D. Goedeke, X-D. Wang, B. Goolsby, V. Dhandapani, L. Prabhu, S. Backer, L-B La, D. Burnett, T. White, B.-Y. Nguyen, B. E. White, S. Venkatesan, J. Mogab, I. Cayrefourcq, C. Mazure, “Strain-Enhanced CMOS Through Novel Process-Substrate Stress Hybridization of Super-Critically Thick Strained Silicon Directly on Insulator (SC-SSOI),” in VLSI symp. Tech. Dig., Jun. 2006, pp.130-131.
[24] T. P. Ma, “Proposes Unipolar CMOS,” Semiconductor International, 2008.
[25] J.-T. Lin, H.-H. Chen, K.-Y. Lu, C.-H. Sun, Y.-C. Eng, C.-H. Kuo, P.-H. Lin, T.-Y. Lai, F.-L. Yang, “Design theory and fabrication process of 90nm unipolar-CMOS,” in Proc. IEEE Int. SNW Conf., 2010, pp.1-2.
[26] C.-H. Sun, J.-T. Lin, H.-H. Chen, Y.-C. Eng, C.-H. Kuo, T.-F. Chang, C.-Y. Chen, P.-H. Lin, H.-N. Chiu, “Numerical study of non-classical unipolar CMOS with different embedded oxide and gate length,” in Proc. IEEE Int. ISNE Conf., 2010, pp.21-24.
[27] 施敏, 伍國鈺 著 張鼎張, 劉柏村譯, 半導體元件物理學. 國立交通大學第三版.
[28] D. A. Neamen 著 楊賜麟 譯, 半導體物理與元件. 倉海書局.
[29] F.-C. Hsu, R. S. Muller, C. Hu, P.-K. Ko, “A Simple Punchthrough Model for Short-Channel MOSFET's,” IEEE Trans. Electron Device, vol. 30, no. 10, Oct. 1983.