當半導體元件尺寸持續微縮，傳統的矽互補式金氧半技術遭遇許多的問題與困難。其中，金氧半場效電晶體需要面對的挑戰是如何有效的控制短通道效應和相關問題，要不然的話，就無法得到良好的元件特性。就矽覆絕緣金氧半場效電晶體來說，因為存在一個埋入氧化層，短通道特性行為相對於矽金氧半元件可以有效的提升。然而，自我加熱效應也由於埋入氧化層存在的關係，使得矽覆絕緣金氧半元件的熱穩定性有所下降。因此，這些挑戰將成為未來平面式金氧半元件持續微縮所需面對的問題。
在本篇論文中，我們提出一個新穎的觀念，叫做“後隔離製程”，主要是把主動區定義的製程挪到源�汲極退火製程之後再去執行。我們也製作兩個新穎的元件，分別為：（一）一個擁有阻隔氧化物、源�汲極束縛點和伴隨額外多晶矽本體之金氧半場效電晶體；（二）一個無阻隔氧化物但有源�汲極束縛點及伴隨額外多晶矽本體之金氧半場效電晶體。實際上，上述兩個架構都可歸類於後隔離類多晶矽薄膜電晶體，這主要是元件擁有多晶矽本體的緣故。然而，就元件繼續微縮來說，我們所提出的架構是可以擁有單晶矽本體作為通道。因此，我們模擬小尺寸的後隔離類矽覆絕緣金氧半場效電晶體作為元件的微縮性能預測。至於實作方面，我們把原有的小尺寸設計改良成適應現有的設備去製作後隔離類多晶矽薄膜電晶體。同時，我們所製作的架構依然保有著額外本體這一特色。
根據模擬結果，我們發現額外矽本體能幫助元件同時抑制短通道效應和自我加熱效應，這主要歸咎於所模擬的元件能夠隔離汲極電場和提升元件的散熱能力。與傳統類矽覆絕緣金氧半元件比較，後隔離類矽覆絕緣金氧半元件呈現較大的閘極漏電流以及寄生電容，但是這些結果依然可以被接受。且實驗結果證實額外之多晶矽本體可以幫助元件對抗電荷共享效應和散熱問題，也就是說一個簡單的後隔離製程不只可以幫助提升性能，亦能降低製作成本。此外，實測也證實有阻隔氧化物比無阻隔氧化物之金氧半元件更能具較佳元件特性。然而，無阻隔氧化物之金氧半元件可以看成是極度微縮後的阻隔氧化物元件，且搭配額外矽本體我們亦能保有一定的元件性能。

As semiconductor device sizes continue to decrease, the traditional bulk CMOS technology is seen as an obstacle itself by the physical device limitations. One of the physical limitations of MOSFETs is to ensure that the SCEs and related issues can be controlled to maintain device performance targets. For SOI MOSFETs, due to the presence of BOX, short-channel behavior is improved, as compared to bulk Si. But self-heating plays a key role in affecting device reliability. Thus, these challenges make the future of planar technology being difficult to be continuously implemented.
In this thesis we introduce the concept of the isolation-last process which moves the “FET active region definition” to the back of the S/D activation process. There are two kinds of devices to be fabricated: BOSDT-APSB MOSFET and ZBOSDT-APSB MOSFET. BOSDT is the acronym of block-oxide S/D-tie and APSB is the acronym of additional poly-Si body. It should be noted that the ZBO is the acronym of zero BO (absence of BO). Actually, the two above-mentioned devices can be referred to as the poly-Si TFTs, due to the presence of poly-Si active region. However, for the ultimate scaling, the two proposed devices can have an additional silicon body or ASB. Two proposed devices, being a consideration of fabrication aspects, have a different design compared to their scaled-down sizes. But we can still hold the ASB’s core values.
According to the simulation, the ASB shows its ability to alleviate the SCEs and offers improved cooling capability, which is because the additional body provides extra space for heat dissipation. The unwanted results are that the large gate leakage current and parasitic capacitances are observed as the ASB is created. Fortunately, these results are still within acceptable limits. Experimental results show that the APSB is desirable to suppress the SCEs in both BOSDT and ZBOSDT MOSFETs. We also verify that the device’s cooling capability can be improved by introducing an APSB into MOSFETs. In other words, the APSB is useful for enhanced performance and reliability, although some disadvantages exist also. The BO has been proven to have a better channel controllability than its counterpart. But the ZBO can be seen as the ultimately scaled BO. And after scaling, the schemes of ZBO and ASB become more pronounced.

1 Introduction--------------------------------------------------------------------------------------1
1.1 Background and Motivation------------------------------------------------------------------1
1.2 Thesis Contribution---------------------------------------------------------------------------20
1.3 Thesis Organization--------------------------------------------------------------------------24
4.3 References-------------------------------------------------------------------------------------25

2 Quasi-SOI MOSFETs with Block-Oxide-------------------------------------------------29
2.1 Introduction------------------------------------------------------------------------------------29
2.2 Development of BO-Based MOSFETs----------------------------------------------------31
2.3 Development of SDT-Based MOSFETs---------------------------------------------------38
2.4 Development of BOSDT-Based MOSFETs-----------------------------------------------43
2.5 Summary---------------------------------------------------------------------------------------47
4.3 References-------------------------------------------------------------------------------------48

3 Device Simulation Setup---------------------------------------------------------------------51
3.1 Introduction------------------------------------------------------------------------------------51
3.2 Physical Models------------------------------------------------------------------------------52
3.3 Advanced Device Fabrication Technology------------------------------------------------57
3.4 Summary---------------------------------------------------------------------------------------61
4.3 References-------------------------------------------------------------------------------------62

4 Simulation Results and Discussion---------------------------------------------------------63
4.1 Introduction------------------------------------------------------------------------------------63
4.2 Characteristics of Isolation-Last QSOI MOSFETs---------------------------------------65
4.3 Summary---------------------------------------------------------------------------------------93
4.3 References-------------------------------------------------------------------------------------94

5 Isolation-Last Quasi-SOI Technology-----------------------------------------------------95
5.1 Introduction------------------------------------------------------------------------------------95
5.2 The BOSDT MOSFET with APSB---------------------------------------------------------97
5.3 The ZBOSDT MOSFET with APSB-----------------------------------------------------103
5.4 Isolation-Last QSOI MOSFETs-----------------------------------------------------------109
5.5 Summary-------------------------------------------------------------------------------------114
4.3 References------------------------------------------------------------------------------------114

6 Experimental Results------------------------------------------------------------------------116
6.1 Introduction----------------------------------------------------------------------------------116
6.2 Device Characteristics of BOSDT-APSB MOSFETs----------------------------------117
6.3 Analog Characteristics of BOSDT-APSB MOSFETs----------------------------------132
6.4 Isolation-Last vs. Conventional Isolation Comparison--------------------------------140
6.5 Summary-------------------------------------------------------------------------------------142
4.3 References------------------------------------------------------------------------------------143

7 Conclusions and Future Work------------------------------------------------------------145
7.1 Conclusions----------------------------------------------------------------------------------145
7.2 Future Work----------------------------------------------------------------------------------147

List of Publications-----------------------------------------------------------------------------150

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