在本論文中，我們提出一個具厚邊襯閘極氧化層負型金氧半負載的高速度非傳統單極性互補金氧半反相器。此非傳統互補金氧半反相器的負載是由一個具貫穿效應的厚邊襯閘極氧化層負型金氧半電晶體取代傳統互補金氧半中的正型金氧半場效電晶體。在論文中主要是探討使用具貫穿效應的厚邊襯閘極氧化層負型金氧半電晶體為負載與負型金氧半場效電晶體為驅動器之非傳統互補式金氧半反相器的特性分析。
根據結果，本論文提出的非傳統互補式金氧半反相器有正確的邏輯特性，平均傳輸延遲與傳統互補式金氧半反相器比較改善20 %，這是因為此非傳統互補金氧半反相器是使用厚邊襯閘極氧化層負型金氧半負載的緣故。在製程上，由於都使用負型金氧半電晶體，在輸出端都是負型摻雜，且不需要N型井的製程。在佈局面積上，此架構擁有共享輸出和無須物理隔離製程，與傳統互補式金氧半反相器比較在佈局面積上可以減少41%，可提升元件的集積密度。

In this thesis, we present a high-speed non-classical unipolar CMOS with a thick sidewall-spacer gate-oxide NMOS load. This unipolar CMOS is composed of a NMOS driver and a thick sidewall-spacer gate-oxide NMOS which replaces a PMOS as load. We focus on the investigation of punch-through current in unipolar CMOS trends. In addition, we also design a conventional CMOS for comparison.
According to the simulations, the logical characteristics of our proposed CMOS are valid, in which the average propagation delay time is improved 20 % compared with the conventional CMOS. This is due to the presence of a thick sidewall-spacer gate-oxide NMOS load. For the viewpoint of device fabrication, the N well process can also be eliminated. This means that the proposed NMOS load not only improves the CMOS speed, but also reduces the fabrication cost. Thus, because of the shared-terminal output, the layout area can be significantly decreased 41 %, in comparison with the conventional CMOS.

第一章 緒論 1
1.1 背景 1
1.2 動機 3
第二章 物理機制與元件操作原理 5
2.1 物理機制 5
2.1.1 貫穿效應 5
2.1.2 汲極和源極空間電荷區 6
2.1.3 閘極控制的空乏層 8
2.1.4 功函數差 8
2.1.5 平帶電壓 9
2.1.6 底限電壓 9
2.2.1 傳統互補式金氧半反相器架構和操作原理 11
2.2.2 厚邊襯閘極氧化層負型金氧半負載之非傳統單極性互補金氧半反相器設計和操作原理 15
第三章 元件架構設計與製程步驟 22
3.1 元件設計 22
3.2 實際製程步驟 23
第四章 結果與討論 26
4.1 元件模擬使用之物理模型 26
4.2 元件模擬電性結果之分析與討論 27
4.2.1 具厚邊襯閘極氧化層負型金氧半負載之非傳統單極性互補金氧半反相器 27
4.3 邏輯電路模擬 38
4.3.1 反或閘 (NOR Gate) 38
4.3.2 反及閘 (NAND Gate) 42
4.3.3 互斥或閘 (XOR Gate) 46
4.3.4 全加器(Full Adder) 48
4.3.5 靜態隨機存取記憶體(SRAM) 50
4.3.6 環形震盪器(Ring Oscillator) 51
4.3.7 品質因子(FOM)比較 55
4.4 佈局(Layout)比較 57
第五章 結論與未來展望 59
5.1結論 59
5.2 未來展望 59
參考文獻 60
附錄 63

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