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博碩士論文 etd-0725112-112632 詳細資訊
Title page for etd-0725112-112632
論文名稱
Title
適用於多媒體應用的多重精確度函數插補器
Multi-precision Function Interpolator for Multimedia Applications
系所名稱
Department
畢業學年期
Year, semester
語文別
Language
學位類別
Degree
頁數
Number of pages
65
研究生
Author
指導教授
Advisor
召集委員
Convenor
口試委員
Advisory Committee
口試日期
Date of Exam
2012-07-17
繳交日期
Date of Submission
2012-07-25
關鍵字
Keywords
多重精確度函數插補器、低功率、閘控時脈、極大極小近似、查表法
minimax approximation, multi-precision function interpolator, look-up table, clock gating, low power
統計
Statistics
本論文已被瀏覽 5673 次,被下載 361
The thesis/dissertation has been browsed 5673 times, has been downloaded 361 times.
中文摘要
本論文提出一個符合IEEE-754單精度浮點數標準的多重精確度函數插補器,它提供對數、指數、倒數,與倒數開根號運算,每種運算都能夠依照需求,動態地選擇四種不同的精確度模式執行。硬體架構採用完全管線化設計,以符合一般數位訊號處理器(DSP)、圖形處理器(GPU)之硬體架構。
考慮到各精確度模式的實用性,在設計之初就盡量降低各精確度模式之間的誤差差距值。在不考慮捨位的前提下,依精確度由高到低,分別提供23、18、13與8位元的精確度。此函數插補器是基於查表法所設計,透過計算二次多項式得到目標函數之近似值,而二次多項式中的係數是利用多區段極大極小近似法獲得。在實做硬體之前,我們使用Maple這套代數軟體產生前述四種運算的二次多項式係數,同時估算產生的係數是否能夠符合IEEE-754單精度浮點數標準。此外,我們採取窮舉法(exhaustive search)檢測硬體之執行結果,確保在各種運算與精確度模式下都能符合要求。
在執行前述四者其中一種運算時,只會使用該運算的表格來獲得二次多項式係數。因此,我們可以利用三態閘作為開關,降低其他三種運算所需之表格的動態功率消耗。除此之外,在執行較低精確度模式時,可以關閉部分用來計算二次多項式的硬體,更進一步提高省電效果。藉由提供多重精確度之硬體,我們希望讓那些以電池當作電源的裝置之使用者或開發人員,能夠在容許的誤差範圍內選擇較低精確度模式,以延長裝置的使用時間。
Abstract
A multi-precision function interpolator, which is fitted in with the IEEE-754 single precision floating point standard, is proposed in this paper. It provides logarithms, exponentials, reciprocal and square root reciprocal operations. Each operation is able to dynamically select four different precision modes in demand. The hardware architecture is designed with fully pipeline in order to comply with hardware architectures of general digital signal processors (DSPs) and graphics processors (GPUs).
When considering the usefulness of each precision mode, it is designed to minimize the error among various modes as far as possible in the beginning. According to the precision from high to low, function interpolator can provide 23, 18, 13 and 8-bit accuracy respectively in spite of the rounding effect. This function interpolator is designed based on the look-up table method. It can get the approximation value of target function through the calculation of quadratic polynomial. The coefficient of quadratic polynomial is obtained by piecewise minimax approximation. Before implementing the hardware, we use the Maple algebra software to generate the quadratic polynomial coefficients of aforementioned four operations, and estimate whether these coefficients can meet IEEE-754 single precision floating point standard. In addition, we take the exhaustive search to check the results generated by our implementation to make sure that it can meet the requirements for various operations and precision modes.
When performing one of the above four operations, only the tables of the operation are used to obtain the quadratic polynomial coefficient. Therefore, we can take the advantage of the tri-state buffer as a switch to reduce dynamic power consumption of tables for the other three operations. In addition, when performing lower precision modes, we can turn off a part of hardwares, which are used to calculate the quadratic polynomial, to save the power consumption more effectively. By providing multi-precision hardware, we hope users or developers, those who use the battery device, can choose a lower precision mode within the permissible error range to extend the battery life.
目次 Table of Contents
摘要 ............................................................................................................................... i
英文摘要 ...................................................................................................................... ii
圖目錄 ......................................................................................................................... vi
表目錄 ....................................................................................................................... viii
第一章 概論 ................................................................................................................ 1
1.1 研究動機........................................................................................................ 1
1.2 論文大綱........................................................................................................ 2
第二章 研究背景 ........................................................................................................ 3
2.1 函數插補器 .................................................................................................... 3
2.1.1 直接查表法 ......................................................................................... 3
2.1.2 著重計算查表法 ................................................................................. 3
2.1.3 折衷方法 ............................................................................................. 4
2.1.4 重複計算法 ......................................................................................... 4
2.2 ..IEEE-754單精度浮點數標準 ....................................................................... 5
2.3 牛頓法 ........................................................................................................... 6
2.4 多項式逼近法 ................................................................................................ 8
2.5 基於二次多項式的函數插補器 ................................................................... 12
第三章 函數插補器架構與實做 ............................................................................... 14
3.1 多項式係數產生 .......................................................................................... 16
3.2 傳統的函數插補器 ...................................................................................... 17
3.2.1 平方器 ............................................................................................... 18
3.2.2 壓縮樹 ............................................................................................... 20
3.2.3 布斯編碼器與部分積選擇器 ............................................................ 23
3.3 多重精確度函數插補器 .............................................................................. 26
3.3.1 以「列」的觀點實現 ........................................................................ 26
3.3.2 以「欄」的觀點實現 ........................................................................ 35
第四章 實驗結果 ...................................................................................................... 41
4.1 實驗步驟與方法 .......................................................................................... 41
4.2 數據比較...................................................................................................... 42
第五章 結論與未來研究方向 ................................................................................... 50
5.1 結論 ............................................................................................................. 50
5.2 未來研究方向 .............................................................................................. 50
參考文獻 .................................................................................................................... 52
參考文獻 References
[1] “IEEE Standard for Floating-Point Arithmetic,” 2008.
[2] 廖英程, “適用於多媒體應用的低功率多重精確度浮點特殊功能運算器,” 國立中山大學資訊工程學系碩士論文, 2009.
[3] U. Kucukkabak and A. Akkas, “Design and implementation of reciprocal unit using table look-up and Newton-Raphson iteration,” Euromicro Symposium on Digital System Design (DSD’04), pp. 249-253, 2004.
[4] J.A. Pineiro, S.F. Oberman, J.-M. Muller and J.D. Bruguera, “High-speed function approximation using a minimax quadratic interpolator,” IEEE Transactions on Computers, vol. 54, no. 3, pp. 304-318, 2005.
[5] J.A. Pineiro, J.D. Bruguera and J.-M. Muller, “Faithful Powering Computation Using Table Look-Up and Fused Accumulation Tree,” IEEE 15th Symp. Computer Arithmetic, pp. 40-47, 2001.
[6] J.A. Pineiro, “Algorithms and Architectures for Elementary Function Computation,” PhD dissertation, Univ. of Santiago de Compostela, 2003.
[7] M.J. Schulte and K.E. Wires, “High-speed inverse square roots, ” IEEE 14th Symp. Computer Arithmetic, pp. 124-131, 1999
[8] R.H. Strandberg, L.G. Bustamante, V.G. Oklobdzija, M.A. Soderstrand and Jean-Claude Duc, “Efficient Realizations of Squaring Circuit and Reciprocal used in Adaptive Sample Rate Notch Filters,” Journal of VLSI Signal Processing, vol. 14, no. 3, pp. 303-309, 1996.
[9] Wen-Chang Yeh and Chein-Wei Jen, “A high performance carry-save to signed-digit recoder for fused addition-multiplication,” IEEE ICASSP, vol. 6, pp. 3259-3262, 2000.
[10] P. Bonatto and V.G. Oklobdzija, “Evaluation of Booth's algorithm for implementation in parallel multipliers,” IEEE Conference on Signals, Systems and Computers (ASILOMAR-29), vol. 1, pp. 608-610, 1996.
[11] Zhijun Huang, “High-Level Optimization Techniques for Low-Power Multiplier Design,” PhD dissertation, Univ. of California, Los Angeles, 2003.
[12] “TSMC 0.13 m (CL013G) Process 1.2-Volt SAGE- Standard Cell Library Databook,” Jan. 2004.
[13] D.-U. Lee, W. Luk, J. Villasenor and P.Y.K. Cheung, “Hierarchical Segmentation Schemes for Function Evaluation,” IEEE International Conference on Field-Programmable Technology (FPT), pp. 92-99, 2003.
[14] S. Erez and G. Even, “An improved micro-architecture for function approximation using piecewise quadratic interpolation,” IEEE International Conference on Computer Design (ICCD), pp. 422-426, 2008.
[15] D.D. Caro and N. Petra, “Elementary Functions Hardware Implementation Using Constrained Piecewise-Polynomial Approximations,” IEEE Transactions on Computers, vol. 60, no. 3, pp. 418-432, 2011.
[16] M. Ercegovac, J.-M. Muller and A. Tisserand, “Simple Seed Architectures for Reciprocal and Square Root Reciprocal,” IEEE Conference on Signals, Systems and Computers (ASILOMAR-39), pp.1167-1171, 2005.
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