在非對稱式密碼系統中，橢圓曲線密碼系統的金鑰長度只要在 160 位元以上就可以達到足夠的安全性強度，相較於其他加解密系統具有較短金鑰長度之優勢，故成為近年來相當熱門的加解密系統。
由於乘法運算是決定橢圓曲線密碼系統效能的主要運算之一，而且它在運算過程中會不斷的執行暫存器位移的動作，消耗的電力將相當可觀。因此本論文基於可調式的序列平行演算法及其架構[1]，提出五種方法來節省乘法器的能量消耗。第一種方法是修改移位暫存器B之架構，並加入一些低功率設計，使其高位元部分的移位頻率得以下降。第二種方法是使用一個除頻電路，並對Reduce-and-AND(RA)架構做一些修改，使RA暫存器可以兩個時脈週期才寫入一次值。第三種方法是加入閘控時脈電路的技術，使暫存器值不變時就不動作。第四種方法是使用省略多餘運算的方法，讓不用做運算的位元跳過，以達到節省時脈週期數的效果。最後一種方法是修改RA電路，使其輸出產能可增加一倍。前三種方法主要著重於低功率的設計，後兩種方法則偏重於效能的改善，而降低功率消耗與提升效能即可節省能量之消耗。最後我們亦利用乘法器面積小的優勢，根據映射座標下的蒙哥瑪利點乘演算法[22][26]，提出了一個Half Cycles的排程版本，此版本的執行效能可比傳統的排程還快一倍。
至於硬體實作部分，所有的模組皆採用階層化的設計，並且使用 CIC 所提供的TSMC 0.13um製程實現。實驗結果顯示，我們提出來的乘法器比傳統的乘法器減少5% ~ 24%的能量消耗。若將低耗能乘法器放入點乘架構中，能量消耗亦可減少12% ~ 47%。由此可知，我們所提出的乘法器版本同時具有低面積複雜度及低耗能的特性，非常適合使用於可攜式電子產品上。

In asymmetric cryptosystems, an important advantage of Elliptic Curve Cryptosystem (ECC) is the shorter key lengths than other cryptosystems. It can provide a level of security when the bit length over than 160 bits. So it has become a popular public key cryptographic system in recent year.
Multiplier needs to run many times in scalar multiplication and it plays an essential role in ECC. Since the registers in multiplier are shifted every iteration, it will consume a lot of power in the computing process. So in this thesis, we propose five methods to save multiplication’s energy consumption based on a scalable serial-parallel algorithm[1]. The first method is to design a low-power shift-register by modifying shift-register B to reduce the frequency of registers shifted. The second method is to use a frequency divider circuit. It can make registers to access a value every two clock cycles by modifying RA units. The third method is to introduce the gated clock circuit, and the clock signal of register will be disabled if its value is the same. The fourth method is to skip redundant operations and it can decrease the number of clock cycles for completing a multiplication operation. The last method raises multiplier’s throughput by modifying RA units. The former three methods focus on low-power design, and the latter two methods emphasize on improving performance. Reducing power consumption and improving performance will save multiplication’s energy consumption. Finally, we propose a Half Cycles schedule to raise scalar multiplication’s performance. It is based on Montgomery scalar multiplication algorithm with projective coordinate[22][26].
For the hardware implementation, TSMC 0.13um library is employed and all modules are organized in a hierarchy structure. The implementation results show that the proposed multipliers have less energy consumption than traditional multiplier. It can get 5% ~ 24% energy saving. For Montgomery scalar multiplication, it can also reduce 12% ~ 47% energy consumption and is suitable for portable electronic products because its low area complexity and low energy.

論文審定書 ................................................................................................................... i
論文提要 ...................................................................................................................... ii
誌謝 ............................................................................................................................. iii
中文摘要 ..................................................................................................................... iv
Abstract ........................................................................................................................ v
目錄 ............................................................................................................................ vii
圖目錄 ......................................................................................................................... ix
表目錄 ......................................................................................................................... xi
第一章 緒論 ................................................................................................................ 1
1.1簡介與動機 ..................................................................................................... 1
1.2論文大綱 ........................................................................................................ 2
第二章 研究背景 ........................................................................................................ 3
2.1密碼系統簡介 ................................................................................................. 3
2.2橢圓曲線密碼系統簡介 ................................................................................. 4
2.2.1數學基礎理論 ...................................................................................... 5
2.2.2有限場基底的基本介紹 ....................................................................... 7
2.2.3 Affine座標架構 ................................................................................... 8
2.2.4 Projective座標架構 ............................................................................. 9
2.2.5點乘演算法 ........................................................................................ 10
2.2.6 ElGamal密碼系統 ............................................................................. 14
2.3基於橢圓曲線之有限場GF(2m)運算單元 .................................................... 15
2.4.1二元體加法運算 ................................................................................ 15
2.4.2二元體乘法運算 ................................................................................ 17
2.4.3二元體平方運算 ................................................................................ 17
2.4.4二元體倒數運算 ................................................................................ 18
第三章 常見的有限場乘法器設計方法 .................................................................... 20
3.1序列乘法器 ................................................................................................... 20
3.2平行乘法器 ................................................................................................... 20
3.3序列平行乘法器 ........................................................................................... 21
第四章 硬體設計與實現 ........................................................................................... 22
4.1橢圓曲線密碼系統的整體架構 .................................................................... 22
4.2位元長度與參數選擇 ................................................................................... 22
4.3二元體運算單元硬體實現............................................................................ 23
4.3.1加法器之硬體實現............................................................................. 23
4.3.2乘法器之硬體實現............................................................................. 24
4.3.3平方器之硬體實現............................................................................. 27
4.3.4倒數器之硬體實現............................................................................. 28
4.4乘法器之低耗能設計 ................................................................................... 29
4.4.1低功率移位暫存器............................................................................. 30
4.4.2除頻電路設計 .................................................................................... 34
4.4.3閘控時脈電路 .................................................................................... 37
4.4.4省略多餘運算 .................................................................................... 39
4.4.5 2-Digit/Parallel乘法器 ....................................................................... 42
4.5 Montgomery點乘硬體實現與新排程 .......................................................... 43
4.5.1傳統的Double_Add排程分析........................................................... 44
4.5.2 Half Cycles版本的Double_Add排程與架構分析 ............................ 45
4.5.3完整點乘運算之架構與Projective to Affine排程架構分析.............. 48
第五章 硬體驗證與實驗數據 ................................................................................... 51
5.1驗證方式 ...................................................................................................... 51
5.2實驗數據分析 ............................................................................................... 52
第六章 結論與未來研究方向 ................................................................................... 54
6.1結論 .............................................................................................................. 54
6.2未來研究方向 ............................................................................................... 55
參考文獻 .................................................................................................................... 56

[1] P.K. Meher and C.-Y. Lee, “Scalable Serial-Parallel Multiplier over GF(2m) by Hierarchical Pre-Reduction and Input Decomposition,” IEEE International Symposium on Circuits and Systems, pp.2910-2913, 2009.
[2] 楊中皇,「網路安全：理論與實務 第二版」,學冠全球資訊網, 2008.
[3] A. Lenstra and E. Verheul, “Selecting Cryptographic Key Sizes,” Journal of Cryptology, vol. 14, no. 4, pp.255-293, 2001.
[4] E. Barker, W. Barker, W. Burr, W. Polk, and M. Smid, “NIST Special Publication 800-57. Recommendation for Key Management–Part 1: General(Revised),” National Institute of Standards and Technology (NIST), 2007.
[5] N. Koblitz, “Elliptic curve cryptosystems,” Mathematics of Computation, vol. 48, no. 177, pp.203-209, 1987.
[6] V. Miller, “Use of Elliptic Curves in Cryptography,” Lecture Notes in Computer Science(CRYPTO’85), vol. 218, pp.417-426, 1985.
[7] J.H. Silverman and J. Tate, “Rational Points on Elliptic Curves. Undergraduate Texts in Mathematics,” Springer-Verlag, New York, 1992.
[8] William Stallings原著, 巫坤品、曾志光譯, 「密碼學與網路安全：原
理與實務第二版」, 碁峰資訊股份有限公司, 2002.
[9] D. Hankerson, A. Menezes, and S. Vanstone, “Guide to Elliptic Curve Cryptography,” Springer-Verlag, New York, 2004.
[10] G. Seroussi, “Table of Low-Weight Binary Irreducible Polynomials,” Computer Systems Laboratory, Hewlett-Packard Company, 1998.
[11] Q. Li, Z. Wang, and X. Liu, “Fast point operation architecture for Elliptic Curve Cryptography,” IEEE Asia Pacific Conference on Circuits and Systems, pp.184-188, 2008.
[12] J.-H. Hong and W.-C. Wu, “The design of high performance elliptic curve cryptographic,” IEEE International Midwest Symposium on Circuits and Systems, pp.527-530, 2009.
[13] S. Moon, J. Park, and Y. Lee, “Fast VLSI Arithmetic Algorithms for High-Security Elliptic Curve Cryptographic Applications,” IEEE Transactions on Consumer Electronics, vol. 47, no. 3, pp.700-708, 2001.
[14] H. Brunner, A. Curiger, and M. Hofstetter, “On computing multiplicative inverses in GF(2m),” IEEE Transactions on Computers, vol. 42, no.8, pp.1010-1015, 1993.
[15] M. Schmalisch, and D. Timmermann, “A reconfigurable arithmetic logic unit for elliptic curve cryptosystems over GF(2m),” IEEE International Symposium on Micro-NanoMechatronics and Human Science, vol. 2, pp.831-834, 2003.
[16] S. Sutikno, A. Surya, and R. Effendi, “An implementation of ElGamal elliptic curves cryptosystems,” IEEE Asia-Pacific Conference on Circuits and Systems, pp.483-486, 1998.
[17] W.El hadj youssef, Z. Guitouni, M. Machhout and R. Tourki, “Hardware implementation of elliptic curve arithmetic in GF(2m),” 4th International Conference on Sciences of Electronic, Technologies of Information and Telecommunications(SETIT), 2007.
[18] H. Wu, “Bit-parallel finite field multiplier and squarer using polynomial basis,” IEEE Transactions on Computers, vol. 51, no. 7, pp.750-758, 2002.
[19] L. Song and K.K. Parhi, “Efficient Finite Field Serial/Parallel Multiplication,” IEEE International Conference on Application Specific Systems, Architectures and Processors, pp.72-82, 1996.
[20] L. Song and K.K. Parhi, “Low-energy digit-serial/parallel finite field multipliers,” Journal of VLSI Signal Processing, vol. 19, pp.149–166, 1998.
[21] M. Hutter, J. Grossschadl, and G.-A. Kamendje, “A Versatile and Scalable Digit-Serial/Parallel Multiplier Architecture for Finite Fields GF(2m),” International Conference on Information Technology: Computers and Communications, pp.692-700, 2003.
[22] P.K. Meher, “High-throughput hardware-efficient digit-serial architecture for field multiplication over GF(2m),” International Conference on Information, Communications & Signal Processing, pp.1-5, 2007.
[23] 徐偉強, 「運用於橢圓曲線加解密系統之高速純量乘法運算架構」, 國立中山大學資訊工程學系碩士論文, 2011.
[24] A. Juristic and A. Menezes, “Elliptic curves and cryptography,” Dr. Dobb’s Journal, 1997.
[25] 陳俊宏, 「橢圓曲線密碼系統之演算法研究與超大型積體電路實現」, 國立雲林科技大學資訊工程學系碩士論文, 2003.
[26] G. Orlando and C. Paar, “A High-Performance Reconfigurable Elliptic Curve Processor for GF(2m),” Proc. Cryptographic Hardware and Embedded Systems (CHES 2000), pp.41-56, 2000.
[27] B. Ansari and M.A. Hasan, “High-performance architecture of elliptic curve scalar multiplication,” IEEE Transactions on Computers, vol. 57, no. 11, pp.1143–1153, 2008.
[28] E. Al-Daoud, R. Mahmod, M. Rushdan, and A. Kilicman, “A new addition formula for elliptic curves over GF(2n),” IEEE Transactions on Computers, vol. 51, no. 8, pp. 972–975, 2002.