本論文採用TSMC 90nm製程技術，在供應電壓1V下，實做一個10位元，8千萬次取樣速率類比數位轉換器。此電路將可用在無線通訊上。
在電路設計上，為了達到高速與高精度，所以設計了使用一次兩位元轉換技術與數位校正的連續漸近式類比數位轉換器架構，其中透過使用動態比較器技術以減少靜態功率消耗，為了達到高速的需求，使用非二進制電容陣列切換方法與數位校正，可在電容穩定前比較，增加可容錯的範圍，以提高類比數位轉換器的轉換速度；並使用對稱式靴帶式交換器以控制前端取樣開關，進而達到減少低電壓操作時對取樣保持電路線性度的影響。
最終本論文提出一個8千萬次取樣率10位元的類比數位轉換器，其中DNL為 +0.997-1 LSB，INL為 +1.351/-1.464 LSB，SFDR與SNDR在尼奎斯特瓶率下為65.453 dB和56.327 dB，ENOB為9.064 bit，功率消耗為2.19 mW，最終FOM為 51 fJ/conv.-step。

In this thesis, a 10-bit, 80 MS/s analog-to-digital converter with a 1 V supply voltage is implemented by using the TSMC 90nm process technology. This circuit can be used in the applications for the wireless communications.
In the circuit design, in order to achieve a higher operation speed and better conversion precision, a 10-bit high speed Successive Approximation Register Analog to Digital Converter with 2 bit per cycle and non-binary digital error correction architecture is proposed by adapting the dynamic comparator techniques to reduce static power consumption. In order to achieve the high-speed operation requirement, the non-binary capacitor array switching and digital correction methods are adapted and it can increase the fault tolerant capability by comparing capacitance before they are stabled. On the other hand, the symmetrical bootstrapping switch is implemented to control the front end sampling switch to improve the conversion speed of the proposed analog-to-digital converter, and thus achieve lowering the non-linearity effects on the sample and hold circuit due to the lowered voltage operation.
This paper presents 80 MS/s and 10 bit analog-to-digital converter, which DNL is + 0.997-1 LSB, INL is + 1.351 / -1.464 LSB, SFDR and SNDR at the Nyquist rate are 65.453 dB and 56.327 dB, ENOB is 9.064 bit, power consumption is 2.19 mW, finally FOM of 51 fJ / conv.-step.
Keywords: Analog to Digital Converter、Successive Approximation Register、2b/Cycle、digital error correction、non-binary digital error correction

論文審定書 i
中文摘要 ii
Abstract iii
Chapter 1 緒論 1
1.1 研究動機與目標 1
1.2 論文章節組織 3
Chapter 2 基本架構介紹 4
2.1 類比數位轉換器(Analog to Digital Converter) 4
2.2 連續漸進式類比數位轉換器(The Successive Approximation ADC) 5
2.2.1 一次一位元轉換連續漸進式類比數位轉換器 5
2.2.2 一次兩位元轉換連續漸進式類比數位轉換器 8
2.3 數位校正方法(Digital Error Correction) 9
Chapter 3 目標架構電路介紹與分析 13
3.1 設計考量 13
3.2 取樣保持電路(Sample and Hold Circuit) 13
3.2.1 電阻值設計考量 14
3.3 MOS開關 15
3.3.1 傳統拔靴帶式開關(Bootstrapped Switch) 15
3.3.2 改良型拔靴帶式開關 17
3.3.3 電荷注入效應(Charge Injection) 20
3.3.4 時脈耦合效應(Clock Feedthrough) 21
3.4 全差動式動態比較器 21
Chapter 4 目標類比數位轉換器之實現 24
4.1 系統架構 24
4.2 目標類比數位轉換器之實現 26
4.2.1 架構介紹 26
4.2.2 比較器與控制電路邏輯 27
4.3 電容陣列數位類比轉換器 28
4.3.1 訊號電容陣列（Signal capacitor array） 28
4.3.2 參考電位電容陣列（VREF capacitor array） 30
4.4 非同步SAR控制電路 31
4.5 數位校正電路 33
4.6 數位碼取代電路 36
4.7 電容與電容陣列電路佈局設計 38
4.7.1 MOS電容 38
4.7.2 MIM電容 39
4.7.3 MOM電容 39
4.7.4 電容陣列設計 40
4.8 類比數位轉換器全電路電路佈局 44
Chapter 5 效能與模擬結果分析 46
5.1 效能測試方法 46
5.1.1 FFT test 46
5.1.2 模擬結果與比較 47
5.1.2.1 靜態分析 48
5.1.2.2 動態分析 50
Chapter 6 結論與未來展望 54
6.1 結論 54
6.2 未來展望 54
Reference 55

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