我們完成了兩種適用於切換電流式的新型電路。 這兩個電路都解決了由於開關切換時
所造成的誤差。 第一個電路是建構在第一代的切換電流式電路並且利用電流補償的技巧。
第二個電路是建構在第二代的切換電流式電路並且利用減少誤差電壓的技巧。
這兩個電路是根據聯華電子公司的0.5μm 製程技術所設計完成的。 在我們的論文中，
第一個電路的精確值可達到 0.1% 的誤差，而且它的頻率是5MHz。 第二個電路的精確值
可達到 0.12% 的誤差，並且它的頻率是 10.5MHz。 我們的結果是利用 SPICE 軟體模擬的。

Two novel clock feedthrough compensation circuits for switched - current (SI) memory cells
are proposed to reduce the clock feedthrough error. One is a current compensation first generation
SI memory cell and another is an error voltage reduction second generation SI memory cell.
Both circuits are designed using a 0.5μm UMC CMOS process. In this study, the first circuit
has obtained an accuracy about 0.1% error with a frequency of 5MHz, and the second circuit has
achieved 0.12% error in accuracy with 10.5MHz in frequency. The results are obtained by SPICE
simulates.

Contents

Ⅰ. Introduction 1

Ⅱ. The First - Generation SI Circuit 3

1. The Conventional First - Generation SI circuit 3

1.1 Clock Feedthrough Error 3

1.2 Output Conductance Error 7

1.3 Mismatch Error 7

2. Previous CFT Cancellation Schemes 9

Ⅲ. The First Novel Switched - Current Circuit 12

1. The Proposed Switched - Current Circuit 12

2. Simulations and Results 16

Ⅳ. The Second - Generation SI Circuit 24

1. The Conventional Second - Generation SI Circuit 24

1.1 Clock Feedthrough Error 25

1.2 Output Conductance Error 26

2. Previous CFT Cancellation Schemes 28

Ⅴ. The Second Novel Switched - Current Circuit 32

1. The Proposed Switched - Current Circuit 32

2. Simulations and Results 36

Ⅵ. Conclusion 40

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