為了有效降低處理器與記憶體間效能的差距，許多研究者提出了一類新型的計算機結構，稱為智慧型記憶體 (Intelligent Memory, IRAM)。本論文將針對其中的一個系統，FlexRAM，設計適用於此種多處理器架構之通訊協定，CPFR (Communication Protocol for FlexRAM)。由於原FlexRAM結構中並沒有完整的提供各處理器間的溝通機制，所以我們在CPFR中，利用原有之共享記憶體特性與通知機制(Notification primitive)，使用軟體的方式，在不更動原架構的條件下，達成各處理器間彼此通訊之目的。此外，為了使程式設計師能順利的在這種系統上撰寫平行程式，我們也提供了一套具有一致性的程式撰寫介面(programming interface)，其使用方式與程式範例在文中將有敘述。

In recent years, many researchers investigated a new class of computer architecture, called intelligent memory (IRAM), to reduce the performance gap between the CPU and memory. In order to increase the flexibility of designing parallel applications, we develop the communication mechanisms for FlexRAM, one of the IRAM architectures. The communication protocol is called CPFR (Communication Protocol for FlexRAM). For the reason of lacking whole communication mechanism in the original FlexRAM architecture, we construct CPFR by using the features of shared-memory and the notification primitive centrally controlled by the main memory processor (P.Mem). In addition, we provide a uniform programming interface in CPFR for the programmers. An example is also used to demonstrate the usage of our communication protocol in detail.

中文摘要………………………………………………………………………………I
英文摘要……………………………………………………………………………II
目錄…………………………………………………………………………………III
圖目錄……………………………………………………………………………IV
表目錄………………………………………………………………………………V
第一章 簡介………………………………………………………………………1
第二章 FlexRAM結構介紹………………………………………………………6
第三章 設計CPFR之動機…………………………………………………………9
第3-1節 問題描述………………………………………………………………9
第3-2節 設計CPFR之動機……………………………………………………9
第3-3節 CPFR之基本概念……………………………………………………9
第3-4節 相關研究……………………………………………………………10
第四章 適合FlexRAM架構之通訊協定的設計………………………………15
第4-1節 設計方法及細節……………………………………………………16
第4-1-1節 P.Array間的處理器通訊模型………………………………16
第4-1-2節 P.Mem間的處理器通訊模型………………………………18
第4-1-3節 CPFR的設計細節及基本資料結構與假設…………………19
第4-2節 CPFR之動作流程…………………………………………………24
第4-2-1節 名詞定義……………………………………………………24
第4-2-2節 CPFR之動作流程…………………………………………24
第4-3節 CPFR程式撰寫介面的設計………………………………………31
第4-4節 MPI和CPFR的比較……………………………………………33
第五章 實驗範例…………………………………………………………………36
第六章 結論………………………………………………………………………41
附錄…………………………………………………………………………………42
參考文獻……………………………………………………………………………52

[1] D. Patterson, T. Anderson, N. Cardwell, R. Formm, K. Keeton, C. Kozyrakis, R. Thomas, and K. Yelick, “A Case for Intelligent RAM,” IEEE Micro, pp.33-44, Mar./Apr. 1997
[2] D. Skillicorn ,and D. Talia, “Models and languages for parallel computation,” ACM Comput. Surv. 30, pp. 123 – 169, Jun. 1998
[3] High Performance Computing Education and Research Center, “Introduction to MPI, ” http://www.arc.unm.edu/workshop/mpi/mpi.html, Dec. 1997
[4] J. Dongarra, S. Otto, M. Snir ,and D. Walker, “A Message Passing Standard for MPP and workstations,” Commun. ACM 39, pp. 84 – 90, Jul. 1996
[5] J. Granacki, et al. , “Data Intensive Architecture: DIVA,” http://www.isi.edu/asd/diva/, 1998
[6] J. Veenstra, and R. Fowler, “MINT: A Front End for Efficient Simulation of Shared-Memory Multiprocessors,” In proc. of MAS-COTS’94, pp. 201-207, Jan. 1994
[7] K. Hwang, “Advanced Computer Architecture: Parallelism, Scalability, Programmability,” McGraw-Hill, pp. 19 – 25, 1993
[8] M. Banikazemi, R. Govindaraju, and R. Blackmore, “Implementing efficient MPI on LAPI for IBM RS/6000 SP systems: Experiences and performance,” In proc. of Parallel and Distributed , pp. 183 –190, 1999
[9] M. Bernaschi, G. Richelli, “MPI collective communication operations on large shared memory systems,” In proc. of Parallel and Distributed Processing’01, pp.159-164, 2001
[10] Message Passing Interface Forum, “MPI:A Message-Passing Interface Standard.” http://www.mpi-forum.org/docs/mpi-11.ps
[11] M. Oskin, F. T. Chong, and T. Sherwood, “Active Page: A Computation Model for Intelligent Memory Computer Architecture,” In proc. of the 25th Annual International Symposium on Computer Architecture, pp. 192 –203, 1998
[12] O. Aumage, G. Mercier, R. Namyst, “MPICH/Madeleine: a true multi-protocol MPI for high performance networks, ” In proc. of Parallel and Distributed Processing Symposium, pp. 479-486, Apr. 2001
[13] R. Brightwell, and A. Skjellum, “MPICH on the T3D: a case study of high performance message passing,” MPI Developer's Conference, pp.2-9, 1996
[14] The MPI Forum, “MPI: A message passing interface,” In proc. of the conference on Supercomputing '93, pp. 878 – 883, 1993
[15] W. Gropp, and E. Lusk, “An abstract device definition to support the implementation of a high-level point-to-point message-passing interface,” Argonne National Laboratory, ftp:// mcs.anl.gov/ pub/ mpi/, Mar. 1995
[16] W. Gropp, and E. Lusk, “MPICH working note: The implementation of the second generation MPICH ADI,” Argonne National Laboratory, ftp:// mcs.anl.gov/ pub/ mpi/, 1993
[17] W. Gropp, and E. Lusk, “The MPI communication library: its design and a portable implementation,” Scalable Parallel Libraries Conference, pp. 160 –165, 1994
[18] W. Gropp, “Tutorial on MPI: The message-passing interface.” Argonne National Laboratory. ftp:// mcs.anl.gov/ pub/ mpi/ tutorial4.ps
[19] W. Gropp, “What is message passing,” Argonne National Laboratory. ftp:// mcs.anl.gov/ pub/ mpi/ class /advancedmpi /mpiprotocols.ppt
[20] Y. Kang, W. Huang, S. Yoo, D. Keen, Z. Ge, V. Lam, P. Pattnaik, and J. Torrellas, “FlexRAM: Toward an Advanced Intelligent Memory System,” In proc. of International Conference on Computer Design , Austin, Texas, Oct. 1999