Responsive image
博碩士論文 etd-0726104-171821 詳細資訊
Title page for etd-0726104-171821
論文名稱
Title
使用PLL之LVDS傳接器中時脈回復及資料回復器
Clock Recovery and Data Recovery Based on PLL for LVDS Transceivers
系所名稱
Department
畢業學年期
Year, semester
語文別
Language
學位類別
Degree
頁數
Number of pages
43
研究生
Author
指導教授
Advisor
召集委員
Convenor
口試委員
Advisory Committee
口試日期
Date of Exam
2004-07-21
繳交日期
Date of Submission
2004-07-26
關鍵字
Keywords
時脈回復器、資料回復器、低電壓差動信號
Clock Recovery, Data Recovery, Low Voltage Differential Signal
統計
Statistics
本論文已被瀏覽 5655 次,被下載 44
The thesis/dissertation has been browsed 5655 times, has been downloaded 44 times.
中文摘要
在本論文中我們提出一種適合用在低電壓差動信號傳輸用的雙邊追蹤時脈資料回復裝置與方法,尤其是關於信號高速傳輸方面,利用鎖相迴路來追蹤眼圖的左眼及右眼,使得資料的取樣信號可以精確地位於眼圖的中心。這樣可以使資料的偵測達到最佳且可以降低資料傳輸時的錯誤率。
Abstract
The topic of this thesis is to propose a dual-tracking clock data recovery device and method for LVDS. Particularly, it is related to a high speed data transmission which utilizes phase-locked loops (PLL) to trace and track two eyes (left eye and right eye), called dual-tracking, to align data sampling at the middle of data eye. Hence, the detection of the data is ensured to be optimal and the BER (bit error rate) is drastically reduced.
目次 Table of Contents
目錄
摘要 i
Abstract ii
第一章 簡介 1
1.1 研究動機 1
1.2 先前文獻探討 2
1.2.1 相關的時脈資料回復電路架構 2
1.3 現有的時脈資料回復電路架構分析 3
1.3.1 Phase picking方式 3
1.3.2 三倍的追蹤取樣架構 4
1.4 論文目的 5
1.5 論文大綱 5
第二章 雙邊時脈追蹤方法與其資料處理流程 7
2.1 簡介 7
2.2 時脈回復及資料回復的流程 9
2.2.1 第一階段: 鎖住輸入參考時脈的相位 12
2.2.2 第二階段: 找出眼圖的左右邊界 12
2.2.3 第三階段: 產生眼圖中心的信號 22
第三章 雙邊時脈追蹤與資料回復的電路設計 23
3.1 簡介 23
3.2 電路設計 23
3.3.1 偏壓產生器 23
3.3.2 電壓控制延遲單元 25
3.3.3 差動信號轉單端信號電路 27
3.3.4 相位頻率比較器 28
3.3.5 充電泵電路 29
3.3.6 DELAY △T延遲產生電路 30
3.3 模擬結果  31
3.3.1 PLL的模擬結果 31
3.3.2 資料回復電路的模擬結果 33
3.4 測試考量  35
3.5 佈局情形  36
3.6 量測結果 37
第四章 結論與相關成果 40

參考文獻 41
參考文獻 References
參考文獻
[1] R. E. Best, Phase-locked Loops. 2nd, New York: McGraw-Hill, 1993.
[2] F. M. Gardner, Phaselock Techniques. New York: Wiley Intersciences, 1979.
[3] V. Kaenel, D. Aebischer, C. Piguet, and E. Dijkstra, “A 320 MHz, 1.5 mW@1.35 V CMOS PLL for microprocessor clock generation,” IEEE J. Solid-State Circuits, vol. 31, no. 11, pp. 1715-1722, Nov. 1996.
[4] S. Sidiropoulos, and M. A. Horowitz, “A semidigital dual delay-locked loop,” IEEE J. Solid-State Circuits, vol. 32, no. 11, pp. 1683-1692, Nov. 1997.
[5] Y. Moon, J. Choi, K. Lee, D.-K. Jeong, and M.-K. Kim, ”An all-analog multiphase delay-locked loop using a replica delay line for wide-range operation and low-jitter performance,” IEEE J. Solid-State Circuits, vol. 35, no. 3, pp. 377-384, Mar. 2000.
[6] C.-M. Hung, and K.-K. O, “A fully integrated 1.5-V 5.5-GHz CMOS phase-locked loop,” IEEE J. Solid-State Circuits, vol. 37, no. 4, pp. 521-525, Apr. 2002.
[7] K. Lee, S. Kim, G. Ahn, and D.-K. Jeong, “A CMOS serial link for fully duplexed data communication,” IEEE J. Solid-State Circuits, vol. 30, no. 4, pp. 353 -364, Apr. 1995.
[8] M.-J. E. Lee, W. J. Dally, and P. Chiang, ”Low-power area-efficient high-speed I/O circuit techniques,” IEEE J. Solid-State Circuits, vol. 35, no.11, pp. 1591-1599, Nov. 2000.
[9] B. Razavi, ”Challenges in the design high-speed clock and data recovery circuits,” Communications Magazine, IEEE, vol.40, no. 8, pp. 94-101, Aug. 2002.
[10] Y. Moon, D.-K. Jeong, and G. Ahn, ”A 0.6-2.5G Baud CMOS tracked 3 × oversampling transceiver with dead-zone phase detection for robust clock/data recovery,” IEEE J. Solid-State Circuits, vol. 36, no. 12, pp. 1974-1983, Dec. 2001.
[11] C.-K. K. Yang, F.-R. Ramin, and M. A. Horowitz, “A 0.5-μm CMOS 4.0-Gbit/s serial link transceiver with data recovery using oversampling,” IEEE J. Solid-State Circuits, vol. 33, no. 5, pp. 713-722, May 1998.
[12] C.-K. K. Yang, and M. A. Horowitz,“ A 0.8-μm CMOS 2.5 Gb/s oversampling receiver and transmitter for serial links,” IEEE J. Solid-State Circuits, vol. 31, no. 12, pp. 2015-2023, Dec. 1996.
[13] K.-Y. K. Chang, J. Wei, C. Huang, S. Li, K. Donnelly, M. Horowitz, Y. Li, and S. Sidiropoulos, “A 0.4-4-Gb/s CMOS quad transceiver cell using on-chip regulated dual-loop PLLs,” IEEE J. Solid-State Circuits, vol. 38, no. 5, pp. 747-754, May 2003.
[14] S.-H. Lee, M.-S. Hwang, Y. Choi, S. Kim, Y. Moon, B.-J. Lee, D.-K. Jeong, W. Kim, Y.-J. Park, and G. Ahn, ”A 5-Gb/s 0.25-/spl mu/m CMOS jitter-tolerant variable-interval oversampling clock/data recovery circuit,” IEEE J. Solid-State Circuits, vol. 37, no. 12, pp. 1822-1830, Dec. 2002.
[15] J. G. Maneatis, ”Low-jitter process-independent DLL and PLL based on self-biased techniques,” IEEE J. Solid-State Circuits, vol. 31, no. 11, pp. 1723-1732, Nov. 1996.
[16] S. Sidiropoulos, High performance inter-chip signaling. Stanford University, USA, Ph.D. thesis, 1998.
[17] B. Razavi, Design of Analog CMOS Integrated Circuits. New York: McGraw-Hill, 2001.
[18] C. Toumazou, G. Moschytz, and B. Gilbert, Trade-offs in Analog Circuit Design. Boston: Kluwer Academic, 2002.
[19] H.-J. Sung; and K. S. Yoon, “A 3.3V CMOS dual-looped PLL with a current-pumping algorithm,” IEICE Trans. Fundamentals, vol. E83-A, no. 2, pp. 267-271, Feb. 2000.
[20] M.-J. E. Lee, W. J. Dally, J. W. Poulton, P. Chiang, and S. E. Greenwood, ” An 84-mW 4-Gb/s clock and data recovery circuit for serial link applications,” in Proc. Symp. on VLSI Circuits, pp. 149-152, June 2001.
[21] C.-C. Wang, C.-L. Lee, J.-F. Huang, and C.-Y. Hsiao, "Clock recovery and data recovery design for LVDS transceiver used in LCD panels," in Proc. Northeast Workshop on Circuits and Systems, June 2004 (NEWCAS 2004, paper no. NC04-108) (accepted).
電子全文 Fulltext
本電子全文僅授權使用者為學術研究之目的,進行個人非營利性質之檢索、閱讀、列印。請遵守中華民國著作權法之相關規定,切勿任意重製、散佈、改作、轉貼、播送,以免觸法。
論文使用權限 Thesis access permission:校內公開,校外永不公開 restricted
開放時間 Available:
校內 Campus: 已公開 available
校外 Off-campus:永不公開 not available

您的 IP(校外) 位址是 18.232.113.65
論文開放下載的時間是 校外不公開

Your IP address is 18.232.113.65
This thesis will be available to you on Indicate off-campus access is not available.

紙本論文 Printed copies
紙本論文的公開資訊在102學年度以後相對較為完整。如果需要查詢101學年度以前的紙本論文公開資訊,請聯繫圖資處紙本論文服務櫃台。如有不便之處敬請見諒。
開放時間 available 已公開 available

QR Code