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博碩士論文 etd-0726104-215721 詳細資訊
Title page for etd-0726104-215721
論文名稱
Title
低電壓差動訊號傳接器
Low Voltage Differential Signaling Transceiver
系所名稱
Department
畢業學年期
Year, semester
語文別
Language
學位類別
Degree
頁數
Number of pages
52
研究生
Author
指導教授
Advisor
召集委員
Convenor
口試委員
Advisory Committee
口試日期
Date of Exam
2004-07-21
繳交日期
Date of Submission
2004-07-26
關鍵字
Keywords
高速、液晶顯示器、低電壓差動訊號、共模負迴授
Low voltage differential signal, High-speed, LCD, Common mode feedback
統計
Statistics
本論文已被瀏覽 5786 次,被下載 50
The thesis/dissertation has been browsed 5786 times, has been downloaded 50 times.
中文摘要
在本篇論文中我們提出了兩種適用於平面液晶顯示器且傳輸速度可達的1.0 Gbps的低電壓差動訊號傳輸裝置。低電壓差動訊號在大尺寸顯示器的高速序列連結上已經成為極受歡迎的訊號傳輸方式。我們提出的設計是資料傳輸速度可達在每秒十億位元而且符合IEEE STD 1596.3-1996 (LVDS)標準的輸出輸入介面電路。在第一種傳送器電路的設計中我們採用穩壓器來隔絕耦合於系統供應電源的雜訊,並且以共模回授的設計來穩定輸出的共模電壓,使其能穩定地落在規格所定義的範圍。在第二種傳送器電路的設計中我們採用直流偏壓的方式來進一步改善共模輸出電壓。此外,在接收器的電路設計中我們使用再生電路在預先放大器與輸出緩衝器之間提供足夠的正回授迴路增益,以正確回復所接收之資料。
Abstract
We propose two kinds of 1.0 Gbps LVDS ( low voltage differential signaling ) transceivers for LCD ( liquid crystal display ) in this thesis. LVDS has become a popular choice for high-speed serial links in large-sized display units. Our designs are an I/O interface circuit for Gbps operation which is fully complied with the IEEE STD 1596.3 (LVDS). A step-down voltage regulator is employed to reject the noise coupled in the system power supply. In the first design of the transmitter, a CMFB (common mode feedback) circuitry is utilized to stabilize the common voltage in a pre-defined range. In the second design of the transmitter, we try to use a DC bias circuitry to stabilize output common mode voltage to further improve the stability of the common mode voltage. By contrast, a regenerative circuit which provides a positive feedback loop gain between the preamplifier and the output buffer in the receiver such that the received bit streams can be correctly restored
目次 Table of Contents
摘要 i
Abstract ii
圖目錄 v
表目錄 vii
第一章 簡介 ..1
1.1 前言 1
1.2 先前文獻探討 3
1.2.1先前相關低電壓差動訊號傳送器架構 6
1.2.2先前相關低電壓差動訊號接收器架構 10
1.3 論文大綱 12
第二章 低電壓差動訊號傳送器電路 14
2.1簡介 14
2.2低電壓差動訊號傳送器原理說明 15
2.3使用共模負迴授之低電壓差動訊號傳送器電路架構設計 16
2.3.1低電壓差動訊號發送器架構 16
2.3.2測試電路 21
2.3.3模擬結果 22
2.3.4預計規格列表 26
2.3.5佈局圖 27
2.3.6晶片照相圖 28
2.3.7量測結果 29
2.4使用直流偏壓之低電壓差動訊號傳送器電路架構設計 31
2.4.1低電壓差動訊號發送器架 31
2.4.2模擬結果 34
2.4.3預計規格列表 38
2.4.4佈局圖 39
第三章 低電壓差動訊號接收器電路 40
3.1 簡介 40
3.2低電壓差動訊號接收器原理說明 40
3.3低電壓差動訊號接收器電路設計 41
3.4 模擬結果 45
3.5 預計規格列表 46
第四章 結論 .47
參考文獻 .49
參考文獻 References
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