由於現今多媒體通訊系統的高速發展，使得系統的複雜度與規模與日俱增，為了因應日趨複雜的系統之即時運算，除了使用超大型積體電路晶片外，隨著積體電路製造技術的進步，使用可重組運算單元增進即時運算能力也逐漸變得可行。可重組運算單元擁有較低研發製作成本與較快研發時間的特色，並比超大型積體電路晶片具有更多的彈性，更適合在非特定的多媒體通訊系統上取得即時運算的優勢，在我們的微顆粒可重組運算單元(Fine-grain Multi-context Reconfigurable Process Unit, FMRPU)中具有多重組態內容的設計，因此在系統重新組態時可取得較快的重新組態時間，本論文介紹可重組運算單元架構下的電腦輔助設計系統環境，針對區塊分割為基礎的佈局與繞線流程，設計可以根據歷史記錄來提高繞線成功率的自動最佳化機制，並從現今各種佈局與繞線演算法中加入區塊分割的元素，形成以區塊分割為基礎的佈局與繞線工具，將叢集運算加上微顆粒可重組單元硬體架構所產生的限制，便可以在微顆粒可重組單元取得正確的區塊分割，透過不斷增加的歷史記錄，對於可繞線參數上限的評估將會越來越接近實際值，大幅度的確保邏輯區塊分割後的可繞性，減少系統在重覆許多不可繞的運算方面耗費大量時間，在佈局方面以模擬冶煉佈局演算法為基礎修正的成本函數，實驗結果顯示本論文修正的佈局成本函數相較於黃子哲之碩士論文[2]中所提到的成本函數能得到大量的改善結果，不僅僅增加可繞線性，亦節省了許多不必要的繞線耗費，在繞線方面以迷宮繞線為變型產生的延遲與擁擠協調繞線演算法是一個非常適用在多個繞線目標與有限繞線資源的可重組運算單元FMRPU上之方法，透過成本函數與繞線花費的重新定義後，可以正確的運作並獲得較低的電路延遲時間。

Due to the rapid development of today’s multimedia communication systems, the complexity and scale of the systems increase day after day. For real-time computing of the systems which become more and more complicated, not only can we use VLSI chips, with the growth of manufacturing techniques of Integrated Circuit, we can apply the Reconfigurable Process Unit to improve real-time computing. Reconfigurable Process Unit is characterized by less cost in research and production as well as less time spent in research and development. Simultaneously, it processes more flexibility than VLSI chips and more suitability in taking advantageous position of real-time computing on an unspecified multimedia communication system. Fine-grain Multi-context Reconfigurable Process Unit has a mechanism of multi-context; therefore, it will take less time when the system reconfigures. This thesis deals with system environment of Computer-Aided Design under the structure of FMRPU, focusing on the placement and routing based on block partition method and designing an automatic optimization mechanism in accordance with historical records to elevate the rate of routable circuit.
With the spirit from various existing algorithm of circuit, we add the factors of block partition, which forms the implements of placement and routing based on block partition. Combined clustering and the limit caused by the hardware structure of FMRRPU, we can have an accurate block partition on FMRPU. Through the continual increase of historical records, the assessment for the upper limit of the argument of routable circuit will get closer to the actual figure. Simultaneously, after the Logic Block Partition, the probability of routable circuit will get great assurance, and the time consumed in lots of repetitious computing on un-routable circuit will decrease. The experimental result reveals that the modified placement cost function can obtain enormous improvement under the comparison with that mentioned the master thesis of Tzu-che Huang. Not only the routability steps up, the unnecessary consumption also reduces largely. In routing, the negotiated congestion-delay algorithm produced on the basis of the transformation of maze routing algorithm has great suitability in the operation on FMRPU, which has many optimization goals and limited routing resource. After the redefinition of the cost function and expenditure for routing, we can operate with accuracy and the time spent on the delayed circuit will decrease.

摘要
ABSTRACT
目錄
圖目錄
表目錄
第一章 簡介
1-1 可重組運算單元的發展與背景
1-2 FMRPU可重組運算系統
1-3 電腦輔助設計工具流程
1-4 研究動機與目的
第二章 相關研究
2-1 FMRPU與商用FPGA之比較
2-2 邏輯區塊包裝演算法
2-3 模擬冶煉佈局演算法
2-4 繞行演算法
第三章 FMRPU硬體架構
3-1 FMRPU基本組成單元
3-2 FMRPU連接網路
3-3 FMRPU特殊運算單元與函式庫
第四章 區塊規劃與分割
4-1 電腦輔助設計軟體流程
4-2 邏輯基本單位規劃與分割
4-3 邏輯陣列規劃與分割
第五章 區塊配置與繞線
5-1 電路延遲評估演算法
5-2 FMRPU模擬冶煉佈局演算法
5-3 FMRPU延遲與擁擠協調繞行演算法
第六章 系統實現與分析
6-1 區塊規劃與分割之實現
6-2 邏輯陣列區塊規劃可繞線率分析
6-3 邏輯基本單位佈局與繞線之實現
6-4 映射電路
6-5 全域佈局與繞線之實現
第七章 結論與未來目標
參考資料
附錄

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