Title page for etd-0726106-125353


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URN etd-0726106-125353
Author Jau-You Chen
Author's Email Address m933010050@student.nsysu.edu.tw
Statistics This thesis had been viewed 4626 times. Download 1194 times.
Department Electrical Engineering
Year 2005
Semester 2
Degree Master
Type of Document
Language zh-TW.Big5 Chinese
Title An automatic optimization mechanism of circuit block partition for Fine-grain Multi-context Reconfigurable Process Unit
Date of Defense 2006-07-17
Page Count 92
Keyword
  • placement
  • routing
  • FMRPU
  • block partition
  • Abstract Due to the rapid development of today‚Äôs multimedia communication systems, the complexity and scale of the systems increase day after day. For real-time computing of the systems which become more and more complicated, not only can we use VLSI chips, with the growth of manufacturing techniques of Integrated Circuit, we can apply the Reconfigurable Process Unit to improve real-time computing. Reconfigurable Process Unit is characterized by less cost in research and production as well as less time spent in research and development. Simultaneously, it processes more flexibility than VLSI chips and more suitability in taking advantageous position of real-time computing on an unspecified multimedia communication system. Fine-grain Multi-context Reconfigurable Process Unit has a mechanism of multi-context; therefore, it will take less time when the system reconfigures. This thesis deals with system environment of Computer-Aided Design under the structure of FMRPU, focusing on the placement and routing based on block partition method and designing an automatic optimization mechanism in accordance with historical records to elevate the rate of routable circuit.
    With the spirit from various existing algorithm of circuit, we add the factors of block partition, which forms the implements of placement and routing based on block partition. Combined clustering and the limit caused by the hardware structure of FMRRPU, we can have an accurate block partition on FMRPU. Through the continual increase of historical records, the assessment for the upper limit of the argument of routable circuit will get closer to the actual figure. Simultaneously, after the Logic Block Partition, the probability of routable circuit will get great assurance, and the time consumed in lots of repetitious computing on un-routable circuit will decrease. The experimental result reveals that the modified placement cost function can obtain enormous improvement under the comparison with that mentioned the master thesis of Tzu-che Huang. Not only the routability steps up, the unnecessary consumption also reduces largely. In routing, the negotiated congestion-delay algorithm produced on the basis of the transformation of maze routing algorithm has great suitability in the operation on FMRPU, which has many optimization goals and limited routing resource. After the redefinition of the cost function and expenditure for routing, we can operate with accuracy and the time spent on the delayed circuit will decrease.
    Advisory Committee
  • Chung-Ping Chung - chair
  • Shie-Jue Lee - co-chair
  • Shen-Fu Hsiao - co-chair
  • Jih-Ching Chiu - advisor
  • Files
  • etd-0726106-125353.pdf
  • indicate access worldwide
    Date of Submission 2006-07-26

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