現今的嵌入式系統的應用愈趨繁雜，其中又以多媒體的應用最受重視，但在嵌入式系統的運作條件下要達到即時多媒體運算是不容易的；目前已有數種方法可以提升多媒體的運算效率，大多是利用異質的協同處理器架構或特定影音編碼/解碼單元的配置來達成目的。本論文提出一個新的架構「多媒體運算暫存器」，以位元切割運算的概念設計整合了暫存器細胞單元和多媒體基礎運算機制（operation pair），此operation pair具位元運算及儲存的能力，以64個operation pairs組合1個具多媒體指令運算能力的多媒體運算儲存單元（MOSU：Multimedia Operation Storage Unit）。MOSU的數量可依系統運算效率的需求做彈性的擴充，利用多個MOSUs和暫存器空間的定址模式的選擇，以達到最佳化的單一指令多筆資料並行（SIMD）的能力。在指令的設計上，以Intel MMX指令集為基礎並依H.26x影像處理特性的效能需求擴充成新的多媒體指令集，提供更佳的多媒體運算支援。在最後的模擬分析中，和Intel MMX指令集相比，設計的多媒體指令集確實有效的提升部分多媒體運算的效率；在整體多媒體運算效率的比較上，和目前知名的Ti C64 DSP相比，也達到105%的運算效率的提升。

Today the application of the embedded system is more complex. Especially the multimedia function is most popular. But it is still difficult to work smooth on the embedded systems. However, there are some solutions to solve this problem, like DSP and some specific codec chips. But these methods are almost outside of the embedded microprocessor. Here we advance a new architecture, Multimedia Operation Register. We use the bit slice concept to design operation pair which combining bit storage cell and bit computation. Sixty four operation pairs form a MOSU（Multimedia Operation Storage Unit）. One MOSU could execute all multimedia instructions. We using multiple MOSUs and three register addressing modes to achieve optimal SIMD. The number of MOSUs in Multimedia Operation Register could be determined flexibly by different kinds of operation efficiency requirement.
On the other hand we design new instruction set based on the Intel MMX instruction set and the operation feature of H.26x video codec series. According to the simulation in 6th chapter, new instruction set is more efficient than the Intel MMX instruction set, and the Multimedia Operation Register architecture compared with C64 DSP could obtain 105% performance enhancement.

摘要 5
ABSTRACT 6
第一章 簡介 13
1-1 研究動機 13
1-2 研究目的 14
1-3 論文架構 14
第二章 相關研究 15
2-1 影像處理運算簡介 16
2-2 Ti C64 DSP架構介紹 24
2-3 Intel MMX指令集 25
2-4 Memory-processer研究 27
2-5 整理與探討 28
第三章 多媒體運算暫存單元設計 31
3-1 多媒體運算暫存器介紹及組成 32
3-2 Operation pairs 34
3-3 MOSU工作流程 36
3-4 記憶體定址方式及多媒體暫存器的群組模式 41
記憶體定址： 41
多媒體暫存器群組模式： 43
3-5 多MOSUs架構 47
第四章 多媒體指令設計 50
4-1 多媒體指令集格式 50
4-2 新多媒體指令設計 52
XSTLW 53
XSTHW 55
XSTLW及XSTHW的應用 55
XSTR4 57
LDSBW 58
LDUBW 59
PADDRB、PADDRW、PADDRD 60
ABSUBB、ABSUBW、ABSUBD、ABSUBQ 61
SELLSAR 62
MOVSAR 63
STSAR 63
第五章 模擬與分析 65
5-1 模擬計算的演算法介紹 65
4×4 DCT 65
RGB轉YCbCr 68
Motion prediction 68
5-2 模擬結果分析 70
4個4×4 DCT 70
2個和4個8×8 SAD 71
320×240 RGB轉換4:2:0 YCbCr 73
Motion prediction 74
平均效率 75
5-3 硬體合成結果 77
5-4 模擬結論 78
第六章 結論 79
參考文獻 80

[1] ITU-T Recommendation H.263 /E 27414, “Video coding for low bit rate communication”, 01/2005.
[2] T. Wiegand, G.J. Sullivan, G. Bjntegaard, A. Luthra, ”Overview of the H.264/AVC video coding standard”, Circuits and Systems for Video Technology, IEEE Transactions on, pp. 560- 576, July 2003.
[3] T. Wedi, “Motion compensation in H.264/AVC”, IEEE Trans. Circuits Syst. Video Technol., vol. 13, pp. 577–586, July 2003.
[4] Iain Richardson：”H.264 / MPEG-4 Part 10 White Paper”, www.vcodex.com.
[5] Texas Instruments, “TMS320C6000 CPU and Instruction Set Reference Guide”, http://www.ti.com/sc/docs/psheets/rel_dsp.htm.
[6] Millind Mittal, Alex Peleg and Uri Weiser, “MMX™ Technology Architecture Overview“, Intel Technology Journal, vol. 1 issue 1, 3rd quarter 1997.
[7] Stefano Tommesani, Intel MMX Instruction Set, http://www.tommesani.com/MMXPrimer.html.
[8] Intel MMX Instruction Set, http://softpixel.com/~cwright/programming/simd/mmx.php
[9] AMD 3DNow! Instruction Set, http://softpixel.com/~cwright/programming/simd/3dn.php.
[10] V. Parthasarathy, A.V. Bharathi and V. Rhymend Uthariaraj, “Performance analysis of embedded media applications in newer ARM architectures”, Parallel Processing, 2005. ICPP 2005 Workshops. International Conference Workshops on, 14-17 June 2005.
[11] Youngsik Kim, Tack-Don Han, Shin-Dug Kim and Sung-Bong Yang, “An Effective Memory--Processor Integrated Architecture for Computer Vision”, International Conference on Parallel Processing (ICPP '97), p. 266, 1997.
[12] David M. Koppelman, “A Multiprocessor Memory Processor for Efficient Sharing And Access Coordination”, Workshop on Mixing Logic and DRAM, International Symposium on Computer Architecture, June 1997.
[13] Henrique S. Malvar, Antti Hallapuro, Marta Karczewicz and Louis Kerofsky, “Low-Complexity Transform and Quantization in H.264/AVC”, IEEE Transactions on circuits and systems for video technology, vol. 13, NO. 7, JULY 2003.
[14] JPEG File Interchange Format version 1.02, http://www.jpeg.org/public/jfif.pdf.
[15] JASWANT R. JAIN, ANIL K. JAIN, “Displacement Measurement and Its Application in Interframe Image Coding”, IEEE Transactions on communications, vol. COM-29, NO. 12, DECEMBER 1981.