p型金屬氧化物半導體在過去三十年來的可靠度，界面狀態密度的產生已成為一個重要元件可靠度問題。界面態的產生可以在元件操作條件下或加速強迫(stress)電壓來達成，例如負偏壓溫度不穩定性(negative bias temperature instability)等。本篇論文中，我們運用了電荷汲引技術(Charge Pumping CurrentTechnology)，去觀察在打入氟離子後的pMOSFET介面狀態密度變少，而且驅動電流增加，原因是起始電壓的下降。隨著氟摻雜濃度越高，NBTI改善越明顯。
由Power Law中，可發現n值都大約為0.25，即符合R-D model，因此可推測在NBTI stress過程中，所以元件受到負偏壓溫度不穩定性的退化現象主要原因為都來自於Si-H斷鍵。另外為了消除製程因素的影響，我們採用外界機械單軸張應力在P型金氧半場效應電晶體來研究負偏壓溫度不穩定性之特性。在單軸張應力下汲極電流與電洞移動率皆減少，且負偏壓溫度不穩定之劣化變得更嚴重。元件受單軸張應力前後，NBTI劣化機制與活化能都符合R-D model。
受雙軸應力下的元件是採用65奈米製程，工業標準化12吋矽晶圓。元件通道平行矽＜110＞方向。另外源/汲極是選擇性磊晶Si1-x Gex ，產生單軸壓應力。外加機械應力是藉由研磨機將基板厚度由800um磨到50um彎曲基板完成。PMOSFET受雙軸壓應力的影響，可以發現汲極電流和電洞移動率同時下降，主要原因是在室溫下有效質量增加，導致移動率下降。
然而，在333K以上現象又相反。因為電洞獲得足夠熱能轉移到更高能階，所以由高能階較低有效質量主導。應變矽被廣泛應用在65奈米技術，應變引致能帶結構改變以提升電子以及電洞移動率。為了要方便應變矽物理機制和可靠性特性，我們提出一個方法，對矽基板採用機械應力以產生通道應變。為了讓通道產生應變，我們選擇利用外界機械應力來彎曲矽基板，此時通道將受到單軸張應力而產生應變。利用彎曲矽基板此方法，我們成功提高SOI NMOSFET的汲極電流與載子遷移率，提升幅度分別為26％與30％。另外，在熱載子效應方面，藉由外界機械應力來彎曲矽基板，我們可以瞭解熱載子效應對應變矽的影響。隨著曲率越大，基板電流有明顯上升的趨勢。

As one of the main sources of instability in p-MOSFETs, interface state (Nit) generation has become an important reliability issue for over three decades.Interface state can be generated gradually under device operational conditions or generated rapidly under accelerated stress such as negative bias temperature instability(NBTI)In this letter,by charge pumping method,it can be seen interface traps are improved after fluorine implant, hence,drain current increases due to VT reduces.NBTI is improved as the dose of fluorine increases.
According to Power Law,the slope (n) of are almost 0.25, and the result is consistent with R-D model.Therefore,the physical mechanism is dominated by Si-H during NBTI stress.In addition,in order to eliminate process issue, an external mechanical uniaxial tensile stress applied on p type metal oxide semiconductor field effect transistors(pMOSFETs) is used for the study of negative bias temperature instability (NBTI)characteristics.Drain current and hole mobility decreases under uniaxial tensile strain,and the NBTI characteristics also become more serious simultaneously.The NBTI degradation mechanism and activation energy are consistent with R-D model before and after applying mechanical stress.
Temperature-dependent biaxial strain effect on p-MOSFETs.The fabrication of devices adopted a commercial 65 nm process on industry standard 12 in.Si wafers, in which the channel direction is parallel to Si＜110＞.Additionally,a selective epitaxial Si1-x Gex source/drain structure was also introduced to form the uniaxial compressive stress.The external mechanical stress was performed by a bending silicon substrate, and the preparation of the bending device is described as follows,the thickness of silicon substrate was reduced from 800 to 50 um by using a Struers RotoPol-21 polisher.
The influence of biaxial compressive stress on p type metal oxide semiconductor field effect transistors MOSFETs was investigated.It was found that drain current and hole mobility of p-type MOSFET with Si1-xGex raised source/drain and external applied mechanical stress significantly decreased due to the increase of effective conductive mass at room temperature.
However,this phenomenon was inverted above 333K.Because the hole can gain enough thermal energy to transmit to a higher energy level by intervalley scattering,its transport mechanism was dominated by lower effective mass at higher energy level.Using strained-silicon this method,we can study the temperature-dependent strain effects and the relationship between strain and electrical characteristics can be also investigated without any process effects.In order to strain the channel,silicon substrate is bent by applying external mechanical stress,the lattice of channel will be strained after applying uniaxial tensile stress.
Therefore,we successfully improve drain current and carrier mobility of SOI NMOSFET,and the increasing rates are 22% and 30% respectively.In addition,we can understand the influence of hot carrier effect on strain silicon by bending silicon substrate with external mechanical stress.With the increase of curvature,substrate current goes up.

目錄................................................................................3
第一章 緒論
1.1 研究背景與動機......................................................................... 17
1.2 有關介面缺陷密度及氧化層電荷密度………………….......... 21
1.3 電荷汲引技術.............................................................................. 23
1.4 有關於負偏壓溫度不穩定性的研究.......................................... 26
1.5 應變矽文獻回顧.......................................................................... 28
1.6 有關絕緣層上矽應變技術之研究.............................................. 34
1.7 絕緣層上矽先進元件製程.......................................................... 35
1.8 部分空乏型與完全空乏型絕緣層上矽比較………………….. 36
1.9 目標…………………………………………………………….. 37
1.10 論文架構……………………………………………………… 40
第二章 量測條件以及參數萃取方式
2.1 量測條件...................................................................................... 41
2.2 參數萃取方式.............................................................................. 42
2.3研磨元件造成應力(Strain)……………………………………... 43
第三章 元件受負偏壓溫度不穩定性之影響
3.1 基本電性...................................................................................... 44
3.2 負偏壓溫度不穩定性………………………………………….. 44
3.3 介電層二氧化矽厚度為1.2nm可靠度之影響.......................... 47
3.4 介電層二氧化矽厚度為6nm可靠度之影響............................. 47
3.5 單軸張應力可靠度之影響.......................................................... 49
3.6 總結.............................................................................................. 50
第四章 雙軸應力下P型金氧半電晶體物理機制探討
4.1 受通道寬度方向單軸張應力PMOSFET的基本電性.............. 76
4.2 受單軸張應力與本質壓應力之馬鞍型PMOSFET基本電性.. 76
4.3 受通道寬度方向單軸壓應力PMOSFET的基本電性.............. 77
4.4 馬鞍型雙軸應力PMOSFET對溫度的關係.............................. 78
4.5 雙軸壓應力下PMOSFET對溫度的關係.................................. 78
4.7 結論.............................................................................................. 81
第五章 具應變技術之SOI金氧半電晶體特性分析
5.1 SOI MOSFET實驗結果與討論................................................... 92
5.2 結論.............................................................................................. 96
參考文獻......................................................................................... 105
圖目錄..............................................................................5
圖3-1-1 Standard與F-Doping 之輸出特性比較圖......................... 51
圖3-1-2 VG-ID(Linear)的Standard與F-Doping 比較圖.................. 51
圖3-1-3 VG-ID(Saturation)的Standard與F-Doping 比較圖............ 52
圖3-1-4 VG-log(ID)(Saturation)的Standard與F-Doping 比較圖.... 52
圖3-1-5 Icp- VG的Standard與F-Doping 比較圖........................... 53
圖3-2-1 STD 強迫(stress)電壓為-1.8V+Vth後其汲極電流對閘極電壓線性關係圖......................................................................................... 53
圖3-2-2 STD強迫(stress)電壓為-1.8+Vth後其汲極電流對閘極電壓對數關係圖............................................................................................. 54
圖3-2-3 摻F強迫(stress)電壓為-1.8V+Vth後其汲極電流對閘極電壓線性關係圖……………………………………………………………. 54
圖3-2-4 Flourine強迫(stress)電壓為-1.8V+Vth後其汲極電流對閘極電壓對數圖............................................................................................. 55
圖3-2-5 High-Dos-F強迫(stress)電壓為-1.8V+Vth後其汲極電流對閘極電壓特性線性關係圖......................................................................... 55
圖3-2-6 High Dos VG電壓為-1.8V+Vth後其汲極電流對閘極電壓對數圖......................................................................................................... 56
圖3-2-7不同元件下強迫(stress)電壓為-1.8V+Vth後其起始電壓對強迫時間..................................................................................................... 56
圖3-2-8 VG為-1.8V+Vth後其起始電壓改變量對強迫時間特性關係圖
………………………………………………………………………. 57
圖3-2-9 Standard的 log(Vth shift) 對log(stress time)特性圖........ 57
圖3-2-10 Flourine的log(Vth shift) 對log(stress time)特性圖........ 58
圖3-2-11 Flourine High Dos的log(Vth shift) 對log(stress time)特性圖
………………………………………………………………………. 58
圖3-2-12 Standard-NBTI後其電荷幫浦電流對脈衝底端電壓特性比較圖......................................................................................................... 59
圖3-2-13 Flourine-NBTI後其電荷幫浦電流對脈衝底端電壓特性比較圖......................................................................................................... 59
圖3-2-14 High Dos-NBTI後其電荷幫浦電流對脈衝底端電壓特性比較圖..................................................................................................... 60
圖3-2-15 Standard NBTI後其IG-VG特性曲線比較圖.................... 60
圖3-2-16 Flourine NBTI後其IG-VG特性曲線比較圖..................... 61
圖3-2-17 Flourine High Dos NBTI後其IG-VG特性曲線比較圖.... 61
圖3-3-1 Standard元件其輸入特性曲線受動態強迫電壓後關係圖
............................................................................................................. 62
圖3-3-2 Flourine元件其輸入特性曲線受動態強迫電壓後關係圖
............................................................................................................. 62
圖3-3-3 High Dos元件其輸入特性曲線受動態NBTI後關係圖
............................................................................................................. 63
圖3-3-4 不同元件其輸入特性曲線受強迫電壓為(-1.8V+Vth) 2000秒後關係圖............................................................................................. 63
圖3-3-5不同元件受強迫電壓為(0.6V+Vth) 4000秒後其輸入特性曲線比較圖. ...............................................................................................64
圖3-3-6不同元件受強迫電壓為(-1.8V+Vth) 6000秒後其輸入特性曲線比較圖................................................................................................. 64
圖3-3-7 薄氧化層DNBTI後起始電壓改變量對時間關係圖 ...... 65
圖3-4-1 Standard元件其輸入特性曲線受動態強迫電壓後關係圖
............................................................................................................. 65
圖3-4-2 Flourine 元件其輸入特性曲線受動態強迫電壓後關係圖
............................................................................................................. 66
圖3-4-3 H-Flourine 元件其輸入特性曲線受動態強迫電壓後關係圖
…………………………………………… …………………………. 66
圖3-4-4 High Dos-NBTI 2000秒後其電荷幫浦電流對脈衝底端電壓特性圖..................................................................................................... 67
圖3-4-5 Flourine-NBTI 2000秒後其電荷幫浦電流對脈衝底端電壓特性圖..................................................................................................... 67
圖3-4-6 High Dos-NBTI 2000秒後其電荷幫浦電流對脈衝底端電壓特性圖..................................................................................................... 68
圖3-4-7 Standard的log(Vth shift) 對log(stress time)特性圖......... 68
圖3-4-8 Flourine的log(Vth shift) 對log(stress time)特性圖.... ...... 69
圖3-4-9 Flourine High Dos的log(Vth shift) 對log(stress time)特性圖
………………………………………………………………………. 69
圖3-4-10 厚氧化層在動態強迫電壓下其起始電壓改變量對強迫時間關係變化圖......................................................................................... 70
圖3-5-1 單軸張應力劣化STD的轉移特性ID(Gm)-VG圖
............................................................................................................. 70
圖3-5-2 單軸張應力劣化STD的起始電壓改變量關係圖............... 71
圖3-5-3 單軸張應力劣化STD的汲極電流百分比關係圖............... 71
圖3-5-4 單軸張應力劣化STD的log(VT) vs log(time)關係圖..........72
圖3-5-5 單軸張應力劣化STD的活化能關係圖............................... 72
圖3-5-6 單軸張應力劣化STD動態起始電壓改變量關係圖........... 73
圖3-5-7 單軸張應力劣化Flourine的轉移特性ID(Gm)-VG圖
............................................................................................................. 73
圖3-5-8 單軸張應力劣化Flourine的起始電壓改變量關係圖......... 74
圖3-5-9 單軸張應力劣化Flourine的汲極電流百分比關係圖.. .......74
圖3-5-10 單軸張應力劣化Flourine的log(VT) vs log(time)關係圖
............................................................................................................. 75
圖3-5-11 單軸張應力劣化Flourine動態起始電壓改變量關係圖
............................................................................................................. 75
圖4-1-1 STD在單軸張應力前後VG-ID(Gm)比較圖
............................................................................................................. 82
圖4-1-2 STD在單軸張應力前後VD-ID比較圖
............................................................................................................. 82
圖4-1-3 STD在不同應變前後之VG-ID比較圖
............................................................................................................. 83
圖4-1-4 STD 在單軸張應力前後不同通道長度之VG-ID比較圖
............................................................................................................. 83
圖4-1-5 STD 在單軸張應力前後不同通道寬度之VG-ID比較圖
............................................................................................................. 84
圖4-2-1 SiGe PMOSFET在雙軸應力前後VG-ID(Gm)比較圖
............................................................................................................. 84
圖4-2-2 SiGe PMOSFET在雙軸應力前後VD-ID 比較圖.................. 85
圖4-2-3 SiGe PMOSFET在雙軸應力前後不同通道長度之VG-ID比較
............................................................................................................. 85
圖4-2-4 SiGe PMOSFET在雙軸應力前後不同通道寬度之VG-ID比較圖
............................................................................................................. 86
圖4-3-1 STD在單軸壓應力前後不同通道長度之VG-ID比較圖
............................................................................................................. 87
圖4-3-2 STD 在單軸壓應力前後不同通道寬度之VG-ID比較圖
............................................................................................................. 88
圖4-3-3 SiGe PMOSFET在雙軸壓應力前後不同通道長度之VG-ID比較
............................................................................................................. 88
圖4-3-4 SiGe PMOSFET在雙軸壓應力前後不同通道寬度之VG-ID比較
............................................................................................................. 89
圖4-4-1 SiGe PMOSFET在雙軸應力前後之VG-ID比較圖............... 89
圖4-4-2 SiGe PMOSFET在雙軸張應力前後之Mobility-Tenperature比較圖..................................................................................................... 90
圖4-5-1 SiGe PMOSFET在雙軸壓應力前後之Mobility-Tenperature比較圖..................................................................................................... 90
圖4-5-2 SiGe PMOSFET在雙軸壓應力前後之Mobility-Tenperature比較圖..................................................................................................... 91
圖5-1-1 SOI不同通道長度下部分空乏型電晶體............................. 97
圖5-1-2 Bulk MOSFET變溫比較ID-VG特性圖
............................................................................................................. 97
圖5-1-3 SOI MOSFET升溫比較ID-VG特性圖
............................................................................................................. 98
圖5-1-4 SOI與Bulk MOSFET在高溫120℃之ID-VG比較圖
............................................................................................................. 98
圖5-1-5 SOI NMOS在應變(Strain)前後之ID-VD比較圖
............................................................................................................. 99
圖5-1-6 SOI NMOS在應變(Strain)前後之線性區ID-VG比較圖
............................................................................................................. 99
圖5-1-7 SOI NMOS在應變(Strain)前後之Gm-VG較圖
............................................................................................................. 100
圖5-1-8 SOI NMOS在應變(Strain)前後變化通道寬度之ID-VG比較圖
………………………………………………………………………. 100
圖5-1-9 SOI NMOS在應變(Strain)前後改變通道長度之ID-VG比較圖
............................................................................................................. 101
圖5-1-10 SOI NMOS在應變(Strain)前後之ID(Gm)-VG飽和區比較圖
............................................................................................................. 101
圖5-1-11 SOI NMOS在應變(Strain)前後之移動率對垂直電場比較圖
............................................................................................................. 102
圖5-1-12 SOI NMOS在應變(Strain)前後室溫之IB-VG比較圖
............................................................................................................. 102
圖5-1-13 SOI NMOS在應變(Strain)前後高溫之IB-VG比較圖
............................................................................................................. 103
圖5-1-14 SOI NMOS在應變(Strain)前後變溫之Isub-VG比較圖
............................................................................................................. 103
圖5-1-15 NMOS在應變(Strain)前後室溫之Isub-VG比較圖
............................................................................................................. 104

表目錄.................................................................................12
表3-2-1 Standard與F-Doping stress前後之參數比較........................ 34
表3-2-2 Standard與F-Doping stress前後之Nit比較
............................................................................................................. 34
表4-1 PMOS(W=10μm、L=1μm STD)彎曲前後(W方向)之參數比較
............................................................................................................. 71
表4-2 PMOS(W=10μm、L=1μm SiGe PMOSFET)彎曲前後(W方向)之參數比較............................................................................................. 75
中文摘要.............................................................................13
英文摘要.............................................................................15

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