正當消費者對於可攜式電子設備功能需求增加以及系統整合技術的成熟，使得嵌入式系統單晶片設計複雜度大幅提升，如此一來，伴隨的是如何效率且精準地驗證如此龐大規模的晶片等課題。本論文將以一ARM7-Like微處理器整合至三維圖形加速器之系統單晶片做為個案研究，從架構設計、系統整合、驗證方法到驗證環境等不同層面逐一探討。
本論文提出一個在系統模型化層級到晶片層級測試樣本均一化的驗證機制，從ESL、RTL到實體FPGA層級，藉由將測試腳本（Test-Bench）行為抽象化，以避免設計者須透過人工的方式來產生不同環境（或層級）所需的測試向量（Test Vector），並且利用版本管理軟體來維護各團隊間的開發進度。此外，事先描述好的測試管理腳本將驗證工作及實驗結果比對機制自動化，不僅增加了回歸測試（Regression Test）過程的效率，晶片開發時程更加能達到上市時機（Time-to-Market）的目標。這樣除了省去手動編輯的時間以及降低錯誤的可能性，可以讓開發者能更專注於演算法設計及功能性驗證。在本晶片開發驗證過程中，曾面臨發展板損壞而必須移植軟硬體環境至新發展平台，應用了上述的驗證方法讓我們能快速的完成平台轉換。
為能夠將系統晶片成果展示於新的雛形化平台－SOCLE MDK-3D上，我們除了修改本系統晶片對外連接通道，同時開發了高效能匯流排橋接器，做為發展平台與系統晶片之間資料交換的用途，透過實現Store & Forward的策略，促進平台與晶片中的兩系統匯流排之溝通效率，並縮短本系統晶片之最長延遲路徑，從先前的82.6MHz提升至120.4MHz的系統工作頻率。

While consumer demand for electronic equipment and more mature systems integration capabilities, it makes the system complexity of chip design increasing significantly. Also accompany an issue is how to efficiently and accurately verify that such a large-scale chip. In this thesis, we make 3D graphics SoC as a case study, investigate the various aspect, i.e. architecture design, system integration, verification methods and verification platform. This thesis proposes a verification methodology with unified test pattern from system modeling level to test chip level, and via increase of the abstraction level of test patterns, that avoided the way through the manual to generate the test patterns. Not only eliminate manual editing effort and reduce the possibility of error, but also allows developers to more focus on algorithm design and functional verification. In addition, through the pre-described of test scenario (Test-bench) which automated verification and comparison methodology. The efficiency of regression test will be increased. And it's much easier to meet the constraint of time to market. However, In order to demonstrate our chip on new prototyping based board. We not only modified the channel of 3DG chip, but also develop a high-performance bus bridge to keep the efficient of exchange data between two system buses which in platform board and our SoC. And shorten the longest path of the overall system so that system clock rate could be enhanced from 82.6MHz to 120.4 MHz system clock rate.

Chapter 1. 3DG SoC Introduction 1
1.1 3DG SoC Overview 1
1.2 3DG SoC Specifications 3
1.3 3DG SoC Architecture 3
1.4 3DG SoC Interface Definition 8
1.5 3DG Processing Flow 12
Chapter 2. Integration of 3DG SoC 14
2.1 Memory Remap Mechanism 14
2.1.1 Problem Statement 14
2.1.2 Software Implementations 14
2.1.3 Hardware Implementations 18
2.2 Design Alternatives 20
2.2.1 Memory Allocation 20
2.2.2 Vector Interrupt Network 21
2.3 Project Management 23
2.3.1 Archives Structure 24
2.3.2 Version Control System 24
Chapter 3. 3DG SoC Verification Methodology 26
3.1 System Modeling Level 27
3.1.1 Introduction 28
3.1.2 Environment Setup 31
3.2 Register Transfer Level 34
3.2.1 Introduction (EASY Platform) 34
3.2.2 Environment Setup (EASY Platform) 36
3.2.3 Introduction (Pattern Generator) 37
3.2.4 Environment Setup (Pattern Generator) 38
3.3 FPGA Emulation Level 40
3.3.1 Introduction (ARM Platform Basedboard) 40
3.3.2 Environment Setup (ARM Platform Basedboard) 42
3.3.3 Introduction (SOCLE MDK-3D EVB) 47
3.3.4 Environment Setup (SOCLE MDK-3D EVB) 48
3.4 3DG SoC Test Patterns 50
3.5 Automatic Verification Mechanism 56
3.6 Verification Results 58
Chapter 4. System Bridge 59
4.1 Basic Bridge 59
4.2 Transfer Response 62
4.3 Store & Forward Bridge（S & F Bridge） 66
4.4 Deadlock Prevention 70
4.5 Critical Path 72
4.6 S & F Bridge with Transfer Separation 74
4.7 Implementation of S & F Bridge 76
4.7.1 I/O Definition 76
4.7.2 Composition 77
4.7.3 Execution Flow 79
4.7.4 Finite State Machine 80
4.8 Verification of S&F Bridge 85
4.9 Experimental Results 86
Chapter 5. Conclusion 92
Chapter 6. Future Work 93
Reference 94
Appendix A. 3DG SoC Register Definition 95
Appendix B. Related Files Structure 104
Appendix C. FPGA Synthesis Results 105
Appendix D. Phisycal Implementation Results 107

[1] L. Cai and D. Gajski, "Transaction Level Modeling: An Overview", Proceeding Hardware/Software Codesign and System Synthesis (CODES+ISSS'03), Oct 2003.
[2] AMBA 2.0 Specification, IHI0011A
[3] F. Vahid and T. Givargis, "Embedded System Design".
[4] M. Keating and P. Bricaud, "Reuse Methodology Manual" (3rd edition).
[5] P. Rashinkar et al., "System-on-a-Chip Verification - Methodology and Techniques".
[6] SystemC-HDL Co-Simulation Manual, Author CoWare, Jul 2007.
[7] ARM, Example AMBA SYstem User Guide ARM DUI0092C
[8] AXD online books
[9] RealView Platform Baseboard for ARM926EJ-S User Guide, Mar 2009 (Rev 8.0)
[10] Versatile/LT-XC2V4000+ Logic Tile User Guide, Oct 2007
[11] RealView LT-XC5VLX330 Logic Tile User Guide, Oct 2007
[12] MDK-3D Ver.1.0 EVB User Manual, Jan 2010 (Rev 1.0)
[13] K. Anjo et al., "Wrapper-Based Bus Implementation Techniques for Performance Improvement and Cost Reduction", Custom LSI Div., NEC Electron. Corp., Kanagawa, Japan; Proceeding Solid-State Circuits, IEEE Journal, May 2004
[14] M. Ebrahimi et al., "Efficient Network Interface Architecture for Network-on-Chips", Dept. of Inf. Technol., Univ. of Turku, Turku, Finland, Proceeding NORCHIP'09, Nov 2009.
[15] C. Spear, "SystemVerilog for Verification"
[16] "Design Vision 2008.09-SP2, Synopsys Inc." http://www.synopsys.com/Tools/Implementation/RTLSynthesis/Pages/default.aspx
[17] "SoC Encounter, Cadence Design Systems Inc." http://www.cadence.com/products/di/soc_encounter/pages/default.aspx