本論文包含兩個主題︰以1倍供應電壓互補式金氧半電晶體製程實現近3倍供應電壓混合電壓共容輸出輸入緩衝器，以及應用於2倍供應電壓輸出緩衝器電壓迴轉率補償之製程、電壓及溫度偵測電路設計。
第一個主題探討一個以1倍供應電壓互補式金氧半製程實現近3倍供應電壓混合電壓共容輸出輸入緩衝器．本設計係以TSMC 0.18 μm CMOS製程實現，利用一動態閘極電壓產生電路來提供堆疊式輸出級電晶體閘極端適當的偏壓，並使用閘極追蹤電路與浮動N井電路，來防止1.8 V元件遇到高電壓時可能發生的閘極氧化層過度應力問題，而且本設計不使用厚氧化層元件，以降低製程成本。本設計可允許�.9 V 至5.0 V之數位訊號傳送或接收。
第二個主題探討一應用於2倍供應電壓輸出緩衝器電壓迴轉率（slew rate）補償之製程、電壓及溫度偵測電路設計。本設計於製程偵測電路部分，分別偵測N型電晶體與P型電晶體所落在的角落。至於電壓及溫度偵測電路部分，則以不同條件下元件充放電導致的時間延遲來做偵測。當2倍供應電壓輸出緩衝器在某些製程、電壓以及溫度不同環境下，輸出級的驅動電流較低或者是較強時，電壓迴轉率控制電路將會補償或是降低其驅動電流，使輸出級的電壓迴轉率維持在一定的變異之內。

This thesis is composed of two parts: a 3×VDD mixed-voltage-tolerant I/O buffer with 1×VDD CMOS standard device, and a PVT detector for 2×VDD output buffer with slew-rate compensation.
In the first topic, a 3×VDD bidirectional mixed-voltage-tolerant I/O buffer, which has been implemented using a typical TSMC 0.18 μm CMOS process, is proposed with a Dynamic gate bias voltage generator to provide appropriate gate drives for the stacked output stage. Besides, a Gate-tracking circuit and a Floating N-well technique are adopted to prevent 1×VDD device from gate-oxide overstress problems and leakage currents. The maximum data rate is simulated to be 166/166/166/100/80 MHz when VDDIO is 5.0/3.3/1.8/1.2/0.9 V, respectively, given an equivalent probe capacitive load of 10pF.
The second topic is a process, voltage, and temperature（PVT）detector for 2×VDD output buffer with slew-rate compensation. The threshold voltage（Vth） of PMOSs and NMOSs varying with process variation could be detected, respectively. In addition, the voltage and temperature variations could be monitored, respectively, by detecting different charging and discharging times of delay buffers at each PVT corner. By adjusting output currents, the slew rate of output signals could be compensated over 24％. Moreover, the maximum data rate with compensation is 133 MHz in contrast with 100 MHz without compensation when VDDIO ＝ 1.8 V, in transmitting mode.

致謝 i
摘要 ii
Abstract iii
目錄 iv
圖目錄 vii
表目錄 x
第一章 概論 1
1.1 前言 1
1.2 相關技術與文獻探討 3
1.2.1 傳統混合電壓共容輸出輸入緩衝器 3
1.2.2 全雙向混合電壓共容輸出輸入緩衝器 5
1.2.3 製程、電壓及溫度變異偵測電路 6
1.2.4 電壓迴轉率控制電路 7
1.3 研究動機 9
1.4 論文大綱 9
第二章 以1倍供應電壓互補式金氧半製程實現3倍供應電壓雙向混合電壓共容輸出輸入緩衝器 10
2.1 簡介 10
2.2 電路架構 10
2.3 電路設計 12
2.3.1 前置驅動電路（Pre-driver） 12
2.3.2 輸出級電路（Output stage） 13
2.3.3 動態閘極偏壓產生電路 13
2.3.4 偏壓產生電路（Bias generator） 15
2.3.5 VDDIO偵測電路（VDDIO detector） 16
2.3.6 Vg1產生電路（Vg1 generator） 16
2.3.7 Vg2產生電路（Vg2 generator） 18
2.3.8 Vg3產生電路（Vg3 generator） 20
2.3.9 Vg4產生電路（Vg4 generator） 23
2.3.10 浮動N井電路（Floating N-well circuit） 24
2.3.11 輸入級（Input Stage） 24
2.3.12 閘極追蹤電路 （Gate-tracking circuit） 25
2.4 電路模擬 26
2.5 預計規格 30
2.6 晶片佈局 30
2.7 晶片實作量測與結果探討 31
第三章 應用於2倍供應電壓輸出緩衝器電壓迴轉率補償之製程、電壓及溫度偵測電路設計 34
3.1 簡介 34
3.2 電路架構 34
3.3 電路設計 36
3.3.1 2倍供應電壓輸出緩衝器（2×VDD output buffer） 36
3.3.2 製程門檻電壓偵測電路 （Process Vth detector） 39
3.3.3 製程編碼產生電路（Pcode & Ncode generator） 42
3.3.4 比較器（Comparator） 43
3.3.5 電壓溫度偵測電路（Temperature & Voltage detector） 43
3.3.6 延遲編碼產生電路（VTcode generator） 44
3.3.7 數位邏輯補償碼產生電路（Digital circuit encoder） 44
3.4 電路模擬 45
3.5 預計規格 52
3.6 晶片佈局 53
3.7 晶片實作量測與結果探討 54
3.8 結果與討論 56
第四章 結論與未來工作 57
參考文獻 58

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