論文使用權限 Thesis access permission:校內立即公開,校外一年後公開 off campus withheld
開放時間 Available:
校內 Campus: 已公開 available
校外 Off-campus: 已公開 available
論文名稱 Title |
應用於OpenGL-ES 2.0 三維繪圖系統整合之跨時脈域匯流排介面設計 Bus Interface Design Between Different Clock Domains and Its Application to OpenGL-ES 2.0 3D Graphics Systems |
||
系所名稱 Department |
|||
畢業學年期 Year, semester |
語文別 Language |
||
學位類別 Degree |
頁數 Number of pages |
89 |
|
研究生 Author |
|||
指導教授 Advisor |
|||
召集委員 Convenor |
|||
口試委員 Advisory Committee |
|||
口試日期 Date of Exam |
2011-01-26 |
繳交日期 Date of Submission |
2011-07-26 |
關鍵字 Keywords |
匯流排、跨時脈域、頂點處理器 vertex shader, Open Core Protocol, OpenGL ES 2.0, AHB, asynchronous bus interface |
||
統計 Statistics |
本論文已被瀏覽 5668 次,被下載 3434 次 The thesis/dissertation has been browsed 5668 times, has been downloaded 3434 times. |
中文摘要 |
本論文實作一個AMBA AHB跨時脈域匯流排介面,透過此介面OpenGL ES 2.0頂點處理器可以在不同的工作頻率下,透過匯流排與其他的硬體元件溝通。在論文中提出三種設計方式,第一種直接以AMBA規範設計跨時脈域包裝器(warpper)。其他兩種方式,為了提高設計的靈活度,以Open Core Protocol(OCP)為基礎,將智慧財(intellectual property,IP)到匯流排的匯流排溝通介面,分為智慧財到OCP,以及OCP到匯流排,兩個介面設計。並將跨時脈域設計加入智慧財到OCP(IP to OCP )介面中,有了跨時脈域 IP to OCP介面,再搭配OCP to AHB介面,就可以將頂點處理器IP以不同頻率在AMBA AHB上工作,此外若將頂點處理器IP到OCP介面,搭配OCP到其他匯流排(如AXI)介面,便可讓同樣的頂點處理器在不同的匯流排架構運作,提高IP設計的重複使用性。 |
Abstract |
Asynchronous bus interface units to AMBA AHB are designed so that an OpenGL ES 2.0 vertex shader can communicate with other hardware units via AHB bus under different working frequencies. The first design is to directly implement an asynchronous AHB wrapper for the vertex shader. The other two designs are based on Open Core Protocol (OCP) to allow for more flexibility. The hardware intellectual property (IP), vertex shader in this thesis, to OCP asynchronous unit is designed so that the IP can be developed independently with different bus protocols as long as the OCP-to-bus interface is provided for a particular bus protocol. With the help of asynchronous IP-to-OCP and OCP-to-AHB interface units, the vertex shader IP can operate at different frequencies from the AHB bus. Furthermore, the same vertex shader (VS) can be connected to other bus protocol (such as AXI) of different frequencies if the OCP-to-AXI interface is provided because the the asynchronous VS-to-OCP have been designed in this thesis. |
目次 Table of Contents |
目 錄 摘 要 .......................................................................................... i Abstract .................................................................................... ii 目 錄 ......................................................................................... iii 圖 次 ......................................................................................... vi 表 次 ......................................................................................... ix 第一章 概論 .............................................................................. 1 1.1 本文大綱 ......................................................................... 1 1.2 研究動機 ......................................................................... 1 1.3 研究貢獻 ......................................................................... 2 第二章 研究背景與相關研究 ................................................... 3 2.1 電腦圖學與OpenGL-ES 簡介 ...................................... 3 2.2 全域跨時脈域局部同步架構簡介 ................................. 7 2.2.1跨時脈域問題 ........................................................... 7 2.2.2解決亞穩態問題 ....................................................... 9 2.2.3解決資料遺失問題 ................................................. 11 2.2.4 GALS結構分類 ..................................................... 13 iv 第三章 AMBA跨時脈域WRAPPER設計 ........................... 16 3.1 AMBA簡介 ................................................................... 16 3.2 AMBA AHB Wrapper設計 ........................................... 18 3.3 跨時脈域AMBA AHB Wrapper設計 ......................... 22 3.3.1非同步FIFO設計 .................................................. 23 3.3.2 AHB 跨時脈域介面寫入動作設計 ...................... 27 3.3.3 AHB 跨時脈域介面讀取動作設計 ...................... 28 3.4 跨時脈域AHB Wrapper與V S整合 ............................. 34 第四章 OCP 跨時脈域INTERFACE設計 .......................... 37 4.1 Open Core Protocol(OCP)簡介 ..................................... 37 4.2 IP to OCP interface設計 ................................................ 41 4.3 IP to OCP 跨時脈域interface設計 ............................. 47 第五章系統比較與驗證 ...................................................... 55 5.1 系統比較 ....................................................................... 55 5.1.1面積分析 ................................................................. 55 5.1.2 Latency分析 .......................................................... 56 5.1.3 Throughput分析 ..................................................... 60 5.2 跨時脈域介面驗證 .................................................... 68 5.3 跨時脈域介面與VS整合驗證................................... 72 第六章 結論與未來目標 ..................................................... 73 6.1 結論 ............................................................................... 73 6.2 設計心得 ....................................................................... 74 6.3 未來目標 ....................................................................... 74 參考文獻: .......................................................................... 75 |
參考文獻 References |
[1] A. Munshi, “Opengl ES Common/Common-Lite Profile Specification”, Ver. 1.1, Nov. 2004. [2] L.Y. Chen, “Software and Hardware Integration of a Programmable Floating- and Fixed-Point Vertex Shader”, National Sun-Yet San University MS Thesis, Jul.2009. [3] ARM Components,Inc. “AMBA Specification Rev2.0” ,May 1999. [4] OCP-IP Association. “Open Core Protocol Specification”, 2001. [5] N.J. Kim, H.J. Lee."Design of AMBA™ wrappers for multiple-clock operations", International Conference on Communications, Circuits and Systems, Vol. 2,pp1438 - 1442,Jun. 2004. [6] C.W. Choi, J. K. Wee, and G. S. Yeon, "The proposed on-chip bus system with GALDS topology" International SoC Design Conference ,Vol. 01 pp294-295,Nov. 2008 [7] M. Krstic , E. Grass , F. K. Gurkaynak, and P. Vivet, "Globally Asynchronous, Locally Synchronous Circuits: Overview and Outlook", IEEE Design & Test of Computers, Vol. 24, no 5, pp430 - 441, Sept.-Oct. 2007 [8] P. Teehan, M. Greenstreet, and G. Lemieux. "A Survey and Taxonomy of GALS Design Styles", IEEE Design & Test of Computers, Vol. 24, Issue 5, pp418 - 428, Sept.-Oct. 2007. [9] Cadence Design System,Inc.“Clock Domain Crossing: closing the loop on clock domain functional implementation problems”,2004. [10] R.W. Apperson, Y. Zhiyi, M.J. Meeuwsen, T. Mohsenin, and B.M. Baas, “ A Scalable Dual-Clock FIFO for Data Transfers Between Arbitrary and Haltable Clock Domains” IEEE Transactions on Very Large Scale Integration Systems, Vol. 15, NO. 10,1125-1133, Oct. 2007. [11] C. E. Cummings, “Simulation and Synthesis Techniques for Asynchronous FIFO Design with Asynchronous Pointer Comparisons,” Synopsys Users Group, 2002. [12] C. E. Cummings, “Synthesis and Scripting Techniques for Designing Multi-Asynchronous Clock Designs,” Synopsys Users Group, 2001. [13] T. Chelcea, and S.M. Nowick, “A Low-Latency FIFO for Mixed-Clock Systems”, Proc. IEEE Computer Society Workshop on VLSI, pp. 119-126.Apr. 2000. [14] J. T. Yantchev, C. G. Huang , M. B. Josephs, and I.M. Nedelchev, “Low-Latency Asynchronous FIFO Buffers ”,Asynchronous Design Methodologies, pp. 24-31 , May 1995. [15] Socle Technology Corporation, “Cheetah Connectivity Specification”,2007. [16] Z. Wang, and O.Hammami, “External DDR2-constrained NOC-based 24-processors MPSOC design and implementation on single FPGA”, International Design and Test workshop,pp.193-197 ,Mar 2008 [17] T.Bjerregaard, S. Mahadevan, R. G. Olsen and J. Sparsø i, “An OCP Compliant Network Adapter for GALS-based SoC Design Using the MANGO Network-on-Chip”, Proc. International Symposium on System-on-Chip,pp171-174,Nov 2005 |
電子全文 Fulltext |
本電子全文僅授權使用者為學術研究之目的,進行個人非營利性質之檢索、閱讀、列印。請遵守中華民國著作權法之相關規定,切勿任意重製、散佈、改作、轉貼、播送,以免觸法。 論文使用權限 Thesis access permission:校內立即公開,校外一年後公開 off campus withheld 開放時間 Available: 校內 Campus: 已公開 available 校外 Off-campus: 已公開 available |
紙本論文 Printed copies |
紙本論文的公開資訊在102學年度以後相對較為完整。如果需要查詢101學年度以前的紙本論文公開資訊,請聯繫圖資處紙本論文服務櫃台。如有不便之處敬請見諒。 開放時間 available 已公開 available |
QR Code |