在高效能積體電路的應用上，金氧半場效電晶體扮演著舉足輕重的角色，原因是因為其本身的低製造成本、低功率消耗以及可微縮化的優點。然而傳統電晶體持續微縮化將面臨短通道效應，甚至閘極漏電等問題，這不但降低閘極控制能力且增加了元件本身的功\\\\率消耗。對於65奈米以下的超大型積體電路應用上，空乏絕緣層覆矽(Silicon on Insulator; SOI)與高介電係數絕緣層/金屬閘極堆疊結構(high-k/metal-gate stacks)技術因此而誕生。在此論文中，我們深入研究新穎金氧半場效電晶體的電性分析和可靠度研究。以元件結構區分，大致上可將本論文分成兩部分，分別為部分空乏絕緣層覆矽(partially depleted SOI)與高介電係數絕緣層/金屬閘極堆疊結構之金氧半場效電晶體。
在部分空乏絕緣層覆矽金氧半場效電晶體這部分，我們首先探討閘極引發浮接基極效應(Gate-Induced Floating Body Effect: GIFBE)的電性，並系統性地研究其物理機制。根據不同的操作的實驗結果顯示，主要物理模型為陽極電洞注入(Anode Hole Injection: AHI)機制，而非一般文獻所提到的價帶電子直接穿遂(Electron Valence Band: EVB)。此外，我們也討論在不同溫度下GIFBE的電性變化，此實驗更驗證了聚積在基板的電洞主要是藉由AHI從多晶矽閘極直接穿遂而來。根據實驗所驗證的AHI物理模型，我們提出一項產生應力的方法來研究GIFBE在受到外界應力的影響。我們發現應力所引發的閘極漏電下降並不會抑制GIFBE的現象，反而使其更加嚴重。根據能帶理論，我們歸納GIFBE變得更嚴重的主要原因，是由於應力造成多晶矽閘極矽能帶窄化，引發AHI碰撞由離所需的能量下降所致。
近年來，在p型電晶體的負偏壓溫度不穩定性(Negative Bias Temperature Instability: NBTI) 扮演著隨時間正常操作下的主要劣化機制。因此，我們接下來將針對p型空乏絕緣層覆矽金氧半場效電晶體，探討GIFBE對負偏壓溫度不穩定性的影響。實驗結果指出GIFBE造成電子累積在基板上，使元件在負偏壓操作下的電場的下降，抑制了NBTI的劣化行為。這些累積在基板電子的來源，部分可歸因於製程所引發的部分n型多晶矽金屬直接穿遂而來。然而根據不同的操作條件，我們提出類似於AHI，稱陽極電子注入(Anode Electron Injection: AEI)的物理模型去解釋大部份的電子在NBTI條件下的產生機制。最後，根據我們提出來的AEI模型，更進一步去研究在GIFBE條件下，外界機械應力對NBTI的劣化情況。
另外一方面，當互補式金氧半場效電晶體微縮至45nm以下時，二氧化矽絕緣層與多晶矽閘極的傳統結構，因閘極漏電過大而無法繼續使用。因此，在本論文的第二部份，我們藉由多種量測方式，如分離式電容-電壓、電荷汲取與直流式量測來建立並分析具有氧化鉿絕緣層/氮化鈦閘極電晶體之電性特性與物理機制研究。實驗結果顯示不同鈦濃度的金屬閘極將影響元件的基本參數，包括起始電壓、載子移動率及次臨界擺幅。此外閘極內部不同的氮濃度也會影響閘極漏電程度與介面缺陷密度。這些現象與氮擴散到高介電閘極層與通道介面有關。
在可靠度方面，由於大量的缺陷存在高介電係數材料本身所造成電荷補獲效應，使得元件本身的起始電壓飄移與驅動電流降低。且元件在實際電路應用上，是處在交流訊號下操作。因此接下來，我們將針對氧化鉿絕緣層/氮化鈦閘極電晶體進行動態偏壓條件下電荷捕獲所引發起始電壓的可靠度研究。同時也比較在靜態偏下元件劣化的情形。實驗結果顯示元件的起始電壓在動態偏壓條件下比靜態劣化的更加嚴重。此外，我們也發現隨著動態頻率的抬升，起始電壓劣化的越明顯。利用分離式電容-電壓量測技術，我們提出電荷捕獲主要發生處為源/汲極與閘極重疊處的說法，提出可能的物理模型，並加以驗證。根據我們提出來的機制，再進一步去探討不同鈦濃度的金屬閘極在動態偏壓條件下的劣化情況。
除此之外，我們更進一步研究在動態偏壓條件下，溫度效應對分別對N型與P型電晶體的起始電壓的影響。實驗結果指出在N型與P型電晶體分別在動態正偏壓(dynamic positive bias)與動態負偏壓(dynamic negative bias)下，隨溫度升高，有一相反劣化趨勢存在。溫度越高，N型電晶體的起始電壓平移將會有降低的現象產生。這主要是由於源/汲極處在高溫下捕獲的電子，有機會藉由熱發射跳躍至導電帶，導致深缺陷捕獲電子的量，隨溫度越高將有下降的現象。而P型電晶體隨溫度越高，有一相反劣化趨勢。這主要是由於高溫下，動態負偏壓所引起的負偏壓溫度不穩定性所造成的結果。
另一方面，在尺寸不斷微縮下，n型熱載子劣化仍是可靠度方面研究的重點。然而，在高介電係數絕緣層/金屬閘極堆疊結構下，熱載子劣化所造成的閘極引發的汲極漏電流(Gate-Induced Drain Leakage: GIDL)在文獻上較少人討論。因此在本論文的最後，我們將研究高介電係數絕緣層/金屬閘極電晶體，n型熱載子效應對GIDL的影響。實驗結果發現GIDL的劣化行為與閘極堆疊結構之介面氧化層厚度有強烈關係。當氧化層介面變薄時，GIDL電流的劣化行為將與傳統電晶體的劣化趨勢相反。根據改變閘極與汲極間的跨壓的實驗結果，我們提出缺陷輔助能帶間穿遂(trap-assisted band-to-band tunneling)的物理模型，來解釋這異常的GIDL劣化行為。最後，我們也進一步去探討不同鈦/氮比例濃度的金屬閘極在熱載子劣化下，GIDL電流的變化情形。發現隨著氮比例的增加，將會抑制GIDL的變化。這主要與氮擴散到高介電層材料內部修補氧空缺，降低高介電層內部缺陷有關。

For the high performance integrated circuits applications such as microprocessors, memories and high power devices, the metal-oxide-semiconductor field effect transistors (MOSFETs) is the most important device due to its low cost, power consumption and scalable property especially. However, the aggressive scaling of conventional MOS devices suffered from noticeable short channel effects such as drain induction barrier lower, punch through, and direct tunneling gate leakage. Those problems not only lower the gate control ability but also increase the standby power consumption. For future VLSI devises below 65 nm regimes, silicon-on-insulator (SOI) and high-k/metal gate MOSFETs are considered to be possible candidates because of faster operation speed and lower power consumption. Therefore, this dissertation investigates the electrical characteristics and reliability issues of novel MOSFETs for 65 nm and below technology. It is roughly divided into two parts, partially depleted (PD) SOI MOSFETs and high-k/metal gate stack MOSFETs, respectively.
In the first part, we systematically investigate the mechanism of gate-induced floating body effect (GIFBE) for advanced PD SOI n-MOSFETs. Based on different operation conditions, it was found that the dominant mechanism can be attributed to the anode hole injection (AHI) rather than the widely accepted mechanism of electron-valence band (EVB) tunneling. Analyzing the GIFBE in different temperature provides further evidence that the accumulation of holes in the body results from the AHI induced direct tunneling current from the poly-Si gate. In addition, we proposed an approach by bending silicon substrate to further study the impact of mechanical strain on GIFBE. The experimental result indicates that the strain effect indeed decreases the gate leakage current, but increases the hole-valence band (HVB) tunneling current, which indicates that GIFBE becomes serious under mechanical strain. Based on our proposed AHI model, this phenomenon can be mainly due to strain-induced band gap narrowing in the poly-Si gate.
In p-type MOSFETs, the reliability issue, named negative bias temperature instability (NBTI), is the dominant degradation mechanism during ON-state operation. Therefore, we also investigate the GIFBE on NBTI degradation for PD SOI p-MOSFETs. The experimental results indicate GIFBE causes a reduction in the electrical oxide field, leading to an underestimate of NBTI degradation. This can be partially attributed to the electrons tunneling from the process-induced partial n+ poly gate. However, based on different operation conditions, we found the dominant origin of electrons was strongly dependent on holes in the inversion layer under source/drain grounding. Therefore, we propose the anode electron injection (AEI) model, similar to anode hole injection model, to explain how this main electron origin is generated during the NBTI stress. Finally, based on our proposed model, we further study influence of mechanical strain on GIFBE for SOI p-MOSFETs.
On the other hand, the SiO2 dielectric and poly-gate are unsuitable for CMOS application below 45 nm technology node due to unacceptable gate leakage current. Therefore, in the second part of this thesis, we investigate the electrical characteristics and physical mechanisms for MOSFETs with HfO2/TixN1-x stacks by using split C-V, DC Id-Vg, and charge pumping techniques. The experimental results indicates that different ratio of Ti strongly affect various parameters, including threshold voltage, mobility, and subthreshold swing, respectively. In addition, the gate leakage current is also strongly dependent on the nitrogen in metal gate. By charge pumping technique, it was found that with increasing Ti concentration of metal gate, there is a trade-off relationship among the interface traps and bulk defects of high-k dielectric. This phenomenon is associated with the amount of nitride diffusion from the metal gate to high-k bulk and SiO2/Si interface layer.
In the aspects of reliability, charge trapping in high-k gate stacks remains an important issue since it causes the threshold voltage (Vth) shift and drive current degradation. This phenomenon can be attributed to a large number of pre-existing traps in the high-k dielectric layer. In real circuit operation, the devices are generally operated in the dynamic condition. Therefore, the following study further investigates Vth instability of Hf-based n-MOSFETs under the dynamic bias operation. The static condition was also performed on the identical device for a comparison. The results indicate threshold voltage (Vth) instability under dynamic stress is more serious than that under static stress, owning to transient charge trapping within high-k dielectric. In addition, the Vth shift clearly increases with an increase in dynamic stress operation frequency. According to these experimental results, we propose a possible physical model for electron trapping phenomena under dynamic stress. Based on our proposed model, we further dynamic stress induced charge trapping characteristics for devices with different Ti1-xNx composition of metal-gate electrodes.
In addition, we further respectively investigates the temperature dependence of dynamic positive bias stress (PBS) and negative bias stress (NBS) degradation in n-type and p-type MOSFETs with high-k/metal gate stacks. The experimental results indicate there is a contrary trend in temperature dependence of Vth shifts for n- and p-MOSFETs under dynamic PBS and NBS, respectively. The Vth shift decreases with increasing temperature for n-MOSFETs under dynamic PBS. This is due to the thermal emission of trapped electrons in high temperature, leading to the reduction in. A contrary trend with temperature for p-MOSFETs under dynamic NBS can be attributed to the interface trap generation induced by NBTI.
On the other hand, hot carrier effect in high-k/metal gate n-MOSFETs was still one of major device reliability concern in device scaling. However, the stress-induced drain leakage current degradation in device with high-k/metal gate stacks has not received as much attention. In fact, the GIDL behavior is associated with phenomenon of charge trapping in high-k dielectric layer. Therefore, the final study is to investigate the effects of channel hot carrier stress (CHCS) on the gate-induced drain leakage current (GIDL) for n-MOSFETs with HfO2/Ti1-xNx gate stacks. It was found that the behavior of GIDL current during CHCS has dependence with the interfacial layer (IL) oxide thickness of high-k/metal gate stacks. As IL thickness becomes thinner, the GIDL current has a gradual decrease during CHCS, which is contrary to the result of thick-oxide IL devices. Based on the variation of GIDL current in different stress voltage across gate and drain terminals, trap-assisted band to band holes injection model was proposed to explain the different behavior of GIDL current for different IL thickness. Furthermore, we also investigated the impact of different Ti1-xNx composition of metal gate electrode on the IGIDL after CHCS, and observed that the magnitude of IGIDL decreases with the increase of nitride ratio. This is due to the fact that nitride atoms diffusing from the metal gate fill up oxygen vacancies, and reduce the concentration of traps in high-k dielectric.

Contents
Abstract (Chinese) i
Abstract (English) v
Acknowledgements xi
Contents .xiv
Figure Captions .xviii
Table Captions xxvii

Chapter 1 Introduction
1.1 General background 1
1.1.1 Overview of Strained Silicon Channel Engineering 2
1.1.2 Overview of Silicon on Insulator Technology 4
1.1.3 Overview of High-k/Metal Gate Stacks Technology 6
1.2 Motivation 7
1.3 Organization of this Dissertation 8
References 11

Chapter 2 Parameter Extraction and Measurement Technique
2.1 Method of Device Parameter Extraction 23
2.2 Principle of Measurement Technique 25
2.2.1 Charge Pumping Measurement 25
2.2.2 Split C-V Technique 28
2.2.3 Pulse I-V Technique 30
Reference 32
Chapter 3 Physical Mechanism of Gate-Induced Floating-Body Effect in Partially Depleted SOI n-MOSFETs
3.1 Introduction 45
3.2 Experiment 46
3.3 Results and Discussion 47
3.4 Summary 51
References 52

Chapter 4 Impact of Uniaxial Strain on GIFBE in Partially Depleted SOI n-MOSFETs
4.1 Introduction 61
4.2 Effects of Strain on the Conduction Band 62
4.3 Experiment 64
4.4 Results and Discussion 65
4.5 Summary 68
References 69

Chapter 5 Gate-Induced Floating Body Effect on NBTI Degradation in Strained PD SOI p-MOSFETs
5.1 Introduction 80
5.2 Mechanism of Negative Bias Temperature Instability 82
5.3 Experiment 85
5.4 Results and Discussion 85
5.5 Summary 91
References 93

Chapter 6 Impact of TixN1-x on Electrical Characteristic in High-k/Metal-Gate MOSFETs
6.1 Introduction 107
6.2 Experiment 110
6.3 Results and Discussion 111
6.4 Summary 119
References 121

Chapter 7 Charge Trapping Induced Frequency-Dependence Threshold Voltage Shift in High-k/Metal Gate n-MOSFETs
7.1 Introduction 139
7.2 Experiment 141
7.3 Results and Discussion 142
7.4 Summary 147
References 149

Chapter 8 Temperature Dependence of Dynamic PBS and NBS Degradation for high-k/metal gate stacks MOSFETs
8.1 Introduction 161
8.2 Experiment 162
8.3 Results and Discussion 163
8.4 Summary 166
References 168

Chapter 9 Hot Carrier Effect on Gate-Induced Drain Leakage Current in n-MOSFETs with HfO2/Ti1-xNx Gate Stacks
9.1 Introduction 175
9.2 Experiment 177
9.3 Results and Discussion 178
9.4 Summary 182
References 184

Chapter 10 Conclusion and Future Work
10.1 Conclusion 193
10.2 Suggestions for Further Study 197

Publication List 199
Vita 203

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