托CMOS積體電路技術進步之福，許多傳統上由BJT類比製程的電路，逐漸的被整合到CMOS電路製程裡。截至目前為止，將數位、類比、甚至高壓元件通通整合至一單晶片(System-on-a-Chip，SoC)之技術已逐漸成熟。為了迎接新技術所帶來的新挑戰，本論文將專注在三個重要的議題上加以討論、設計、與實作，並希望提供能夠重複使用之設計方法。
本論文第一個主題探討自動增益控制器之理論與實作。在電路實現的部分，包含了一分貝線性可變增益放大器、高輸入輸出擺幅之可變增益放大器、雙偵測單儲存峰值偵測器、前授輸出擺幅自動增益控制器、與可程式化增益放大器。
第二個主題探討高壓製程電路的研製。本主題涵蓋了將低電壓類比訊號轉成高電壓高擺幅訊號之運算放大器與一串聯式電池充電電路。另外，關於高壓製程之相關特性，在本論文裡一併加以討論。
最後一個主題專注於底板收發器之設計，包含了一預加重發送器與判斷回授平等化接受器之電路實作。發送器電路之傳送速度可高達每秒500 Mbps，接收器之接收速度則約125 Mbps。

Thanks to the advance in CMOS technology, an extensive category of applications has been migrated from traditional BJT-based processes. System-on-a-Chip (SoC) realization of digital, analog, and even high voltage devices is now a reality. To address the challenge imposed by integrating analog and high voltage devices in standard CMOS processes, this thesis aims at the design of three specific topics in particular.
With regard to the contents of the thesis, first of all, the theory of linear-in-dB automatic gain control (AGC) is discussed. In succession, a linear-in-dB variable gain amplifier (VGA) is mentioned. The implementation of a Feed-forward Output Swing Prediction AGC featuring a Prediction Parallel-Detect Single-Store Peak Detector (PDSSPD) and a High Input/Output Swing VGA is also described. Furthermore, a digitally programmable gain amplifier for a ZigBee wireless receiver is also mentioned.
In response to the advent of CMOS-compatible high voltage tolerant Bipolar-CMOS-DMOS (BCD) process, an operational amplifier for level converting operation is disclosed. A 60-V Li-ion battery charger has also been proposed, along with a novel battery charge mode, namely, the incremental charge (IC) mode. Practical issues regarding the high voltage tolerant BCD process is also briefly discussed.
Finally, a backplane transmitter featuring pre-emphasis and a receiver utilizing decisive feedback equalization (DFE) designed for CIC MorPack technology are presented. When packaged in a Leadless Ceramic Carrier (LCC) package, the transmitter can transmit up to 500 Mbps and the receiver can receive up to 125 Mbps, both through DuPont connectors without impedance matching.

Contents
Acknowledgement i
摘要 (Mandarin Abstract) iii
Abstract iv
Contents v
List of Figures ix
List of Tables xiv
Chapter 1: INTRODUCTION 1
1.1 Motivation 1
1.2 Overview 3
1.2.1 Automatic gain control circuits 3
1.2.2 High voltage integrated circuits 4
1.2.3 Backplane transceivers 5
1.3 Prior Arts 6
1.3.1 AGC, VGA, and PGA 6
1.3.2 High voltage designs using LDMOS 8
1.3.3 Charger operation 10
1.3.4 Transceiver systems 15
1.4 Overview of the Thesis 18
Chapter 2: AGC 21
2.1 Constant Settling Time AGC 21
2.2 A Linear-in-dB VGA 24
2.2.1 Approximation of exponential gain characteristics 24
2.2.2 VGA circuit with exponential gain characteristics 28
2.2.3 Measurement results of the VGA 33
2.3 An AGC with FROST and PDSSPD 39
2.3.1 Low power implementation of an AGC 39
2.3.2 Feed-forward output swing prediction (FROST) 40
2.2.3 Parallel-detect single-store peak detector (PDSSPD) 41
2.3.4 Proposed VGA 46
2.3.3 Implementation Results 47
2.4 1-dB Gain Step PGA 53
2.4.1 Implementation of a ZigBee receiver 53
2.4.2 Operational amplifier 54
2.4.3 Multiple feedback filter 55
2.3.4 Design of a programmable gain amplifier 57
2.5 Summary 63
Chapter 3: HV IC DESIGN 65
3.1 High Voltage IC Design Overview 65
3.3.1 0.25 μm BCD 60 V process overview 65
3.3.2 Voltage signal conversion 67
3.2 DIFC Amplifier 69
3.2.1 Small-signal design 69
3.2.2 Circuit level design 73
3.2.3 Simulation of a DIFC amplifier 76
3.3 60 V Charger Design 79
3.3.1 Charger architecture 79
3.3.2 Embodiment of the proposed charging solution 80
3.3.3 IC, CC, and CV charge modes 81
3.3.4 CV loop and diode-based CC clamp 83
3.3.5 CV loop and diode-connected load as CC clamp 80
3.3.6 Incremental current loop 88
3.3.7 Over-temperature protection 92
3.3.8 Antenna effect protection PAD 94
3.3.9 Implementation 96
3.4 Summary 101
Chapter 4: MORPACK TRANSCEIVERS 102
4.1 Fundamentals of Backplane transceivers 102
4.1.1 Uni-polar/differential signaling at high frequency 102
4.1.2 Skin effect 106
4.1.3 Eye diagram and inter-symbol interferences 108
4.2 CIC MorPack Transmitter Design 110
4.2.1 Pre-emphasis 110
4.2.2 A transmitter with pre-emphasis 111
4.2.3 Simulation of the transmitter with pre-emphasis 115
4.2.4 Measurement of the transmitter with pre-emphasis 116
4.3 CIC MorPack Receiver Design 118
4.3.1 Decision feedback equalizer 118
4.2.2 A DFE receiver 120
4.2.3 Simulation of the DFE receiver 123
4.2.4 Measurement of the DFE receiver 123
4.4 Summary 119
Chapter 5: CONCLUSION AND FUTURE WORK 126
References 129

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