單晶片多核心處理器(Chip Multiprocessor)已成為現今處理器設計的主流。傳統單晶片多核心系統中，單晶片多核心處理器能透過內部的單一處理器核心架構來探勘指令層級並行度(Instruction Level Parallelism, ILP)，並且能透過多顆處理器的並行運算來探勘執行緒層級並行度(Thread Level Parallelism, TLP)。然而傳統單晶片多核心架構必須在硬體設計規劃之初，在高單一執行緒效能與高生產量做取捨，無法動態的調整指令層級並行度與執行緒層級並行度的探勘能力，造成了目前單晶片多核心處理器面對未來多變的應用程式類型處理上的效率不彰。
因此本論文所使用的架構基礎名為超多純量（Hyperscalar）架構，此架構是一種單晶片多核心的微處理器系統架構，能動態群組多顆處理器核心為一個運算能力較高之超純量核心，而重新組態的特性讓多核心處理架構擁有高度彈性，當執行緒層級並行度低時，透過多核心共同運行而提高單一執行緒效能，反之則透過多核心獨立運作提供高生產量。
為了使處理器使用效率提升，將動態偵測執行緒的ILP變化，使得系統可依照指令並行度高低來群組或釋放處理器群。本論文以Hyperscalar為基礎，加入判斷執行緒並行度機制，並使用新增的兩道指令CRM(Core Register Move)和RelC(Release Core)釋放處理器核心。CRM指令能將資料從要被釋放掉的核心搬移到此群組的其他核心中，以確保釋放核心後群組內的資料正確性；RelC指令表示將此顆核心釋放，當此指令到達WB stage會發送release訊號給群組管理核心單元，告知核心已完全清空且資料全數轉移完成。群組管理核心單元派發這兩道指令後，系統即可依據執行緒並行度來釋放或群組核心數量。經過實測結果可達到處理器使用率的提升以及整體工作效率的提升。

Current trends in processor design have migrated toward chip multiprocessors (CMPs). CMPs are designed to exploit both instruction-level parallelism (ILP) within processors and thread-level parallelism (TLP) within and across processors. However, the conventional design of current CMPs is forced to make a choice between high single-thread performance and high peak throughput. This inability to adjust to varying levels of ILP and TLP results in processor inefficiency.
Therefore, this paper is based on the hyperscalar architecture which is a chip multiprocessor. The hyperscalar concept enables the multi-core architectures to dynamically group many scalar in-order cores as a superscalar processor to accelerate a sequential thread. The reconfigure feature of hyperscalar architecture contributes to the high flexibility in adapting different types of applications, providing high single-thread performance when thread level parallelism (TLP) is low and high throughput when TLP is high.
In order to increase the efficient of the processors, the system will dynamically detect the ILP of the thread. And according to the difference of the ILP, it will group or release the processors. Based on the hyperscalar architecture, this thesis adds the mechanism which can detect the ILP of thread. And the two new instructions CRM (Core Register Move) and RelC (Release Core) can release the processors of the group. To ensure the data accuracy within the group after release the core, CRM instruction move the information from the core which is released to the other core in this group; RelC instruction indicates to release the core. When this instruction executes in the WB stage, it will send a release signal to Group-Management-Unit (GMU) to notify the data has been completely transferred and the core is empty. After GMU dispatches these two instructions, the system will release or group the cores according to the ILP. Simulation results show that the proposed architecture can increase the use of the processors and improve the work efficiency.

論文審定書 i
致謝 ii
中文摘要 iii
Abstract iv
圖片列表 viii
表格列表 x
第一章 簡介 1
1.1 研究動機 1
1.2 研究目標 2
1.3 論文架構 3
第二章 相關研究 4
2.1 單一核心架構介紹 4
2.2目前多核心處理器架構 6
2.2.1 多核心增進多執行緒效能之架構 6
2.2.2 多核心增進單執行緒效能之架構 7
2.3 超多純量(Hyper-scalar)架構介紹 14
2.2.1 指令分析器 16
2.2.2 虛擬共享暫存器檔案 19
2.2.3 Register data flow的處理 21
2.2.4 Memory data flow的處理 23
2.2.5 Instruction flow的處理 25
第三章 設計於超多純量架構下以偵測執行緒並行度之優化群組管理核心 28
3.1 具優化群組管理核心之超多純量系統架構 28
3.1.1系統架構設計概念 28
3.1.2 系統架構 29
3.2 系統操作模式 30
3.2.1 處理器群組方式 30
3.2.2 新增指令 30
3.3 群組管理核心單元 33
3.4 資訊處理單元 38
3.5 指令運作範例 43
第四章 模擬與分析 50
4.1架構模擬 50
4.1.1模擬器架構之程式碼流程 50
4.1.2 判斷ILP之程式碼流程 52
4.1.3效能評估模擬方法 52
4.1.3效能評估程式 54
4.2模擬結果 55
4.2.1 不同效能評估程式在不同核心數目下之ILP 55
4.2.2加入優化群組管理核心單元架構與超多純量架構效能增進關係 55
第五章 結論 57
參考文獻 59

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