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博碩士論文 etd-0726113-124007 詳細資訊
Title page for etd-0726113-124007
論文名稱
Title
應用電力線通訊於Homeplug AV 之設計與實現
The Design and Implement of Homeplug AV Using Power Line Communication
系所名稱
Department
畢業學年期
Year, semester
語文別
Language
學位類別
Degree
頁數
Number of pages
67
研究生
Author
指導教授
Advisor
召集委員
Convenor
口試委員
Advisory Committee
口試日期
Date of Exam
2013-07-17
繳交日期
Date of Submission
2013-08-26
關鍵字
Keywords
交錯器、正交振幅調變、渦輪編碼、電力線通訊、攪亂碼
Turbo encoder, Scrambler, Power line Communication, Interleaver, QAM
統計
Statistics
本論文已被瀏覽 5726 次,被下載 161
The thesis/dissertation has been browsed 5726 times, has been downloaded 161 times.
中文摘要
隨著科技時代的進步與通信技術的快速成長,電力線通訊(PLC)的技術已經從低速進步到高速傳輸,主要是利用電力線來發送載波信號。電力線通訊是利用現有的電力線來傳輸資料、數據、語音之媒介的一種通訊方式,因此它具有許多優點,如低成本、範圍廣、即插即用、不需要額外佈線,只要有插頭就可以使用電力線來傳送訊號。

本論文著重於電力線通訊系統之實體層硬體設計於實現, 參考HomePlug AV
所定義之實體層通訊技速規格,內容包含有攪亂編碼跟渦輪編碼,交錯器及正交振幅調變,首先,我們完成每個區塊的系統模擬跟設計,並驗證每個區塊接收機跟傳送機,以實現完整之基頻通訊系統架構。

關鍵詞:電力線通訊、攪亂碼、渦輪編碼,交錯器,正交振幅調變
Abstract
The rapid growth of communication technology with advances in technology, the technology advance of power line communication (PLC) has been from low speed to high speed transmission. Power line communications (PLC) uses the existing power lines as a data transmission medium and data, digital media. Therefore, it has many advantages, such as low-cost, wire wide range, plug and play, mobile convenient, just plug the device into will transmit over the power line.

In this thesis, it mainly focuses on the implementation with design of the physical layer of power line communications (PLC) system according to HomePlug AV specification. The contents are scrambler and descrambler, turbo encoder and turbo decoder, interleaver and deinterleaver, QAM. First, we finish the system simulation in each block, and confirm that the system receiver and transmitter verification, to complete baseband communication system.





Keywords: Power line communications (PLC), scrambler, turbo-encoder, interleaver, QAM.
目次 Table of Contents
CONTENTS
PAGE
CHAPTER 1 INTRODUCTION 1
1.1 Motivation 1
1.2 Thesis Organization 3
CHAPTER 2 HOMEPLUG AV BACKGROUND 5
2.1 HomePlug AV Introduction 5
2.2 HomePlug AV Standard 8
2.3 PLC Modulation Schemes 9
2.3.1 Single-carrier Modulation 9
2.3.2 Multi-carrier Modulation 15
2.4 Orthogonal Frequency-Division Multiplexing 16
2.5 Homeplug AV Characteristics 17
CHAPTER 3 HOMEPLUG AV SYSTEM 19
3.1 HPAV System Architecture 19
3.2 Data Rate Calculate 20
3.3 Homeplug AV PLC Baseband Circuit 21
3.4 HomePlug AV Specification 23
3.5 Summary 24
CHAPTER 4 HPAV TRANSMITTER AND RECEIVER 25
4.1 Data Scrambler / Data Descrambler 25
4.2 Turbo Encoder / Turbo Decoder 26
4.2.1 Recursive Systematic Convolutional Code 27
4.2.2 Viterbi Decoder 28
4.3 Interleaver / Deinterleaver 29
4.4 QAM 31
4.5 IFFT / FFT 37
4.6 Guard Interval 40
CHAPTER 5 SIMULATION RESULT 42
5.1 Data Scrambler / Data Descrambler Simulation 42
5.2 Turbo encoder / Turbo decoder Simulation 44
5.2.1Convolution code simulation / Viterbi Decoder simulation 44
5.2.2 Turbo encoder simulation/ Turbo decoder simulation 45
5.3 Interleaver / Deinterleaver Simulation 46
5.4 QAM Simulation 47
5.5 Summary 50
CHAPTER 6 CONCLUSION AND FUTURE WORK 53
6.1 Conclusion 53
6.2 Future Work 53
Reference 55














LIST OF FIGURES
PAGE
Figure 1.1 Spectral occupancy of standard North American mask.. 3
Figure 2.1 HomePlug transmission. 6
Figure 2.2 HPAV access system modules in CSMA 7
Figure 2.3 Single carrier transmission. 10
Figure 2.4 ASK modulation.. 10
Figure 2.5 FSK modulation 11
Figure 2.6 PSK modulation 11
Figure 2.7 The waveforms in the transmitters 12
Figure 2.8 Feedback shift register 13
Figure 2.9 State of shift resister 13
Figure 2.10 DSSS transmitter 14
Figure 2.11 DSSS receiver 14
Figure 2.12 DSSS waveforms 14
Figure 2.13 FHSS transmitter 15
Figure 2.14 FHSS receiver 15
Figure 2.15 Multicarrier carrier transmission. 16
Figure 2.16 OFOM system model 17
Figure 3.1 HPAV transmitter and receiver. 22
Figure 3.2 The entire verification flow of IC 24
Figure 4.1 Scrambler architecture 25
Figure 4.2 Descrambler architecture 26
Figure 4.3 Turbo encoder architecture. 27
Figure 4.4 Turbo decoder. 27
Figure 4.5 convolution code 28
Figure 4.6 convolution code state diagram 28
Figure 4.7 Viterbi decoder state diagram 29
Figure 4.8 Interleaving by a memory and registers 30
Figure 4.9 Deinterleaving process 31
Figure 4.10 16-QAM constellation diagram 33
Figure 4.11 64-QAM constellation diagram 33
Figure 4.12 256-QAM constellation diagram 33
Figure 4.13 1024-QAM constellation diagram 34
Figure 4.14 16-QAM noise constellation diagram 34
Figure 4.15 64-QAM noise constellation diagram 34
Figure 4.16 256-QAM noise constellation diagram 35
Figure 4.17 1024-QAM noise constellation diagram 35
Figure 4.18 QAM theoretical 35
Figure 4.19 QAM transmitter. 37
Figure 4.20 QAM receiver. 37
Figure 4.21 3072FFT flow. 48
Figure 4.22 Guard interval with zero padding 40
Figure 4.23 Inter-symbol interference 41
Figure 5.1 Simulation result of data scrambler 42
Figure 5.2 Simulation result of data descrambler 43
Figure 5.3 The verify flow scramble of this design 43
Figure 5.4 Simulation result integration of descrambler and scrambler 43
Figure 5.5 Simulation result of convolution 44
Figure 5.6 Simulation result of viterbi 44
Figure 5.7 The verify flow convolution and viterbi of this design 44
Figure 5.8 Simulation result integration of convolution and viterbi 45
Figure 5.9 Simulation result of turbo encoder 45
Figure 5.10 Simulation result of turbo encoder 46
Figure 5.11 Simulation result of interleaver 46
Figure 5.12 Simulation result of deinterleaver 47
Figure 5.13 1024-QAM constellation 48
Figure 5.14 Simulation result of 1024-QAM 48
Figure 5.15 Simulation result of 1024-DEQAM 49
Figure 5.16 The verify flow QAM of this design 49
Figure 5.17 Simulation result integration of 1024-QAM and 1024-DEQAM 49
Figure 5.18 Simulation result of transmitter 50
Figure 5.19 Simulation result of receiver 50
Figure 5.20 Synthesis circuit diagram 51
Figure 5.21 Synthesis area diagram 51
Figure 5.22 Synthesis power diagram 52
Figure 5.23 Synthesis time diagram 52

LIST OF TABLES
PAGE
Table 1.1 Transmit spectrum limits. 2
Table 2.1 Comparison of Narrowband PLC and Broadband PLC. 9
Table 3.1 HPAV Symbol characteristics. 20
Table 3.2 Bits/Subcarrier Symbol transform. 22
Table 3.3 Date rate with different coding rate and mapping. 22
Table 3.4 HomePlug AV SPES. 26
Table 4.1 Applications for different modulation. 32
Table 4.2 QAM bandwidth efficiency. 36
參考文獻 References
[1] H. C. Ferreira, J. Newbury, and T. G. Swart, “Power Line Communications: Theory and Applications for Narrowband and Broadband Communications over Power Lines,” WILEY, pp. 363-390, 2010.
[2] Mark E. Hazen, “The Technology Behind HomePlug AV Powerline Communications,” Computer, vol. 41, no. 6, pp. 90-92, June 2008.
[3] S. Gall, O. Logvinov, “Recent Developments in the Standardization of Power Line Communications within the IEEE,” IEEE Communication Magazine, pp. 64-71, 2008.
[4] 李淑敏、郭可驥、王朝欽與陳朝順,2008,節能通信 IC 晶片開發與智慧型電能管理系統整合研究,NSC98-2220-E-110-009。
[5] Mortharia Meftah, Laurent Toutain, David Ros,Abdesselem Kortebi, “ NS-2 Model of HomePlug AV PLC Technology,”.
[6] HomePlug 1.0 Specification, HomePlug Powerline Alliance, 2001.
[7] HomePlug AV Specification, HomePlug Powerline Alliance, 2006.
[8] HomePlug AV2 Specification, HomePlug Powerline Alliance, 2012.
[9] HomePlug Technical Paper, “HomePlug Green PHY Overview,” Atheros Communications, pp. 4-11, 2010.
[10] Narrowband Powerline Communication Applications and Challenges.
[11] S. Haykin, Communication Systems, 4th ed. Wiley and Sons, 2001.
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[16] 陳後守、邱茂清、王忠炫、吳昭明, 錯誤更正碼. 臺北市: 教育部顧問室, 2007。
[17] M. S. John G.Proakis, Digital Communications. McGraw Hill, 2008.
[18] Manjunatha K N, Kiran B, Prasanna Kumar.C, “Design and ASIC Implementation of a 3GPP LTE-Advance Turbo Encoder and Turbo Decoder,” vol. 2, issue 4, pp. 006-010, July-August 2012.
[19] C.-L. T. J.-J. T. Shung-Chih Chen, Chao-Tang Yu, “A new ifft/fft hardware implementation structure for OFDM applications,” The proceedings of 2004 IEEE Asia-Pacific Conference on Circuits and System, vol. 2, pp. 1093–1096, 2004.
[20] H. F. Chi and Z. H. Lai, “A Cost-Effective Memory-Based Real-Valued FFT and Hermitian Symmetric IFFT Processor for DMT-based Wire-Line Transmission Systems,” in Proc. IEEE International Symposium on Circuits and Systems, vol.6, pp. 6006-6009, 2005.
[21] Anindya Majumder and J. James Caffery, “Power line communications: an overview,” Potentials, IEEE, vol. 23, no. 4, pp. 4-8, Oct.2004.
[22] “IEEE Standard for Broadband over Power Line Networks: Medium Access Control and Physical Layer Specifications,” IEEE Communi- cations Society, IEEE Std. 1901-2010, December 2010.
[23] Shin-Chieh Hsu,“Study and FPGA Implementation of Powerline Communication System Using OFDM Signals,” Thesis for Master of Science, National Cheng Kung University, pp. 2-10, Jun 2004.
[24] 鈦思科技,通訊系統設計與模擬使用MATLAB/Simulink. 臺北市: 鈦思科技股份有限公司, 2007。
[25] David astelow, Andrew Logothetis and Marlon Persaud, ”Extension of OFDMA Physical layer mode to support 256 & 1024 point QAM constellations for high capacity back-haul applications,” March 2013.
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