於近代熱門的積體電路設計與製造因為其相關產品廣泛的應用範圍與其可觀的利潤而吸引多人紛紛投入。然而隨著積體電路製造技術的進步，技術的開發碰觸到一個極限而使電路系統的製造良率下滑。對於許多需要精密運算的軍事和航太工業發展而言，電路的製造良率對這些領域的應用具有直接的影響。本研究以影像處理電路為例，配合影像處理及其他電路設計與測試的觀念提出一套可以提升影像處理電路良率及可靠度的硬體設計架構。藉由計算電路錯誤的發生率以及錯誤嚴重程度來評估晶片的可使用性，並將影像處理領域中的影像增強觀念納入設計的考量，使設計的系統除了能應用在一般無誤的影像外；亦能夠針對有誤電路所產生的錯誤影像進行處理使輸出結果盡可能接近人類視覺系統所能接受的範圍，藉由這樣的方法使得雖有錯誤但不嚴重的影像解碼器能夠加以運用而不致丟棄，進而提升晶片有效良率。在實驗結果中可以發現當影像解碼器在明亮度資料輸出發生錯誤且發生在最低有效位元附近四位元時，則輸出影像在視覺品質上都能為人眼接受；另一方面，不同明亮度資料錯誤的影像能在系統中經過適度的影像增強處理來改善影像的品質。在此論文中我們亦實現出一個影像增強處理電路之雛型以便在影像增強電路之效能及實用性上進行初步的評估。邏輯合成結果顯示此電路可在10 MHz的操作頻率下有效提升影像之品質，而面積約為37,757個邏輯閘的大小。

With the shrinking of the feature size of transistors, chips become more sensible to manufacturing defects and/or external noises, which may cause low manufacturing yield. In this thesis, we propose a methodology for improving yield and reliability of image processing circuits. By carefully evaluating and analyzing image quality, the proposed methodology can not only improve the quality of an error-free image, but also reduce the error significance of an unacceptable erroneous image so as to maximize their acceptability in a certain application. The experimental results show that minor variations in image are almost insensible and one can easily increase the acceptability of an image using an appropriate image enhancement method. In this thesis we also implement a prototype of an image enhancement circuit to preliminarily evaluate the performance and practicability of image enhancement hardware. The logic synthesis results show that the implemented circuit can effectively enhance the quality of images at the operating frequency of 10 MHz, and the area is approximately 37,757 logic gates.

論文審定書 i
誌謝 ii
中文摘要 iii
英文摘要 iv
圖次 vi
表次 viii
第一章 導論 1
第二章 相關技術發展近況 4
2.1 容錯設計簡介 4
2.2 容誤設計簡介 5
2.3 內建自我測試技術 6
2.4 影像增強技術 10
第三章 影像處理電路良率與可靠度提升方法 15
3.1 影像處理電路發生錯誤的可能情形 15
3.2 系統設計架構 16
3.3 影像增強演算法介紹與程式設計 22
3.4 影像增強系統設計 25
第四章 實驗與模擬結果 38
4.1 有誤影像解碼器對影像品質的影響 38
4.2 影像增強系統的軟體設計及分析 39
4.3 影像增強系統的電路合成結果 54
第五章 結論與未來展望 56
5.1 結論 56
5.2 未來研究規劃 56
參考文獻 57

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