在現今的系統晶片設計中，唯讀記憶體(Read Only Memory, ROM)扮演一個很重要的角色。由於ROM擁有架構規則的特性，ROM元件通常是透過ROM編譯器或產生器產生。例如ARM TSMC的細胞庫提供ROM編譯器自動合成ROM的任意尺寸。一般而言，有兩種不同實作類型，如傳統ROM架構或是可程式化邏輯陣列(Programmable logic array, PLA)。為了實現傳統ROM架構，我們採取動態NAND型態的電路設計，並使用多層次的解碼器以減少面積成本。關於PLA則是使用NOR-NOR型態架構，並利用Espresso邏輯最小化之工具將邏輯積項優化。我們將開發一個可自動產生兩種ROM架構的ROM產生器，產生後的ROM與ARM提供的ROM編譯器以及直接使用RTL(Register Transfer Level)撰寫組合邏輯電路並透過Synopsys Design Compiler合成的ROM。至於ROM在不同尺寸下面積、延遲與功率消耗，我們找到了一些有趣的觀察，並嘗試去改進我們的ROM自動產生器，使他們合成較大尺寸的ROM更有競爭力。

Read-only memory (ROM) plays an important role In modern System-on-Chip (SoC) designs. Due to the regularity of ROM structure, ROM components are usually generated through automatic ROM compiler/generator. For example, ARM TSMC cell library provides ROM compiler to automatic synthesize ROM of arbitrary size. In general, there are two different types of ROM implementations, conventional ROM structure or programmable logic array (PLA). For the implementation with the conventional ROM structure, we adopt the dynamic NAND-based circuit design with multi-level decoder to reduce the area cost. Regarding PLA-based implementation, the dynamic NOR-NOR structure is used where the logic optimization of product terms is performed using the Espresso logic minimization tool.We develop automatic ROM generators for both ROM structures and make comparison with those obtained from ARM ROM compiler and those directly synthesized from combination logic using Synopsys RTL (Register Transfer Level) Design Compiler. Based on the extensive comparisons of area, delay and power for ROM in various sizes, we make several interesting observations, and try to improve our ROM generators in order to make them more competitive for synthesis of large ROM size.

第1章 導論 1
1.1 研究動機 1
1.2 論文組織 2
第2章 唯讀記憶體與相關文獻 3
2.1 唯讀記憶體架構 3
2.1.1 列解碼器 5
2.1.2 行解碼器 7
2.1.3 記憶體元件陣列 9
2.2 可程式化邏輯陣列架構 10
第3章 唯讀記憶體自動產生器 15
3.1 自動產生器流程說明 15
3.2 CIF佈局檔 16
3.3 周邊電路設計 17
3.3.1 解碼器電路設計 18
3.3.2 預先充電電路設計 20
3.3.3 記憶體細胞元設計 20
3.4 電路佈局規劃 21
3.5 數據比較 26
第4章 可程式化邏輯陣列自動產生器 30
4.1 自動產生器流程說明 30
4.2 Espresso化簡 31
4.3 周邊電路設計 36
4.3.1 積陣列 36
4.3.2 內部緩衝器 37
4.3.3 和陣列 38
4.4 電路佈局規劃 38
4.5 數據比較與分析 46
第5章 比較分析與改進 50
5.1 面積分析 50
5.2 延遲分析 53
5.3 功率消耗分析 54
5.4 改進與效果比較 56
第6章 結論與未來目標 64
6.1 結論 64
6.2 未來目標 64
參考文獻 65

[1] Neil H. E. Weste and D. Harris, IntegratedCircuit Design(4th Edition).2011
[2] J. M. Rabaey, A. Chandrakasan, and B. Nikolic, “Digital Integrated Circuits: A Design Perspective,”(Prentice Hall Electronics and VLSI Series, 2003, 2nd edn.)
[3] Jinn-Shyan Wang et al., Member, “Analysis and Design of High-Speed and Low-Power CMOS PLAs,” IEEE Journal of Solid-state Circuits, vol. 36, no 8, August 2001.
[4] G. M. Blair,“PLA design for single-clock CMOS,”IEEE J.Solid-State Circuits, 1992,vol 27, no. 8, pp. 1211-1213.
[5] Y. B. Dhong and C. P. Tsang,“High speed CMOS POS OKA using pre-discharged OR array and charge sharing AND array,” IEEE Trans. Circuits Syst. II, vol. 39, pp. 557-564, Aug. 1992.
[6] C. C. Wang, C. F. Wu, R. T. Hwang, and C. H. Kao,“A low power and high-speed dynamic PLA circuit configuration for single-clock CMOS,” IEEE Trans. Circuits Syst. I, vol. 46, pp. 857-861, July 1999.
[7] Kwang-Il Oh andLee-Sup Kim, “A High Performance Low Power Dynamic PLA with Conditional Evaluation Scheme,”IEEE ,2004.
[8] Chiuan-Tai Xiao and Kai-Cheng Wei, “Using the Charge Recycling Technique for Low Power PLA Design,” IEEE,2010.
[9] M. Yamaoka et al.,“90-nm Process-Variation Adaptive Embeddeed SRAM Modules With Power-Line-Floating Write Technique,”IEEE Journal of Solid-state Circuits, vol. 40, no.3,Mar. 2006.
[10] M. Yamaoka et al., “SRAM Design on 65-nm CMOS Technology With Dynamic Sleep Transistor for Leakage Reduction,”IEEE Journal of Solid-state Circuits, vol. 40, no.4, Apr. 2005.
[11] H. Jiao and V. Kursun, “Ground Bouncing Noise Suppression Technique for Data Preserving Sequemtial MTCMOS Circuits,” IEEE Trans. Very Large Scale Integr.(VLSI) Syst, vol. 19, no.5, May. 2011
[12] James T. Kao and P. Chandrakaasan, Member, “Dual-Threshold Voltage Technique for Low-Power Digital Circuits,”IEEE Journal of Solid-state Circuits, vol. 35,no. 7,July 2000.
[13] Chua-Chin et al., “A Low Power High-Speed 8-bit Pipelining CLA Design Using Dual-Threshold Voltage Domino Logic,” IEEE Trans. Very Large Scale Integr.(VLSI) Syst, vol. 16, no.5, May. 2008.
[14] 吳普誠, “低功耗多讀寫埠記憶體之實作及在繪圖處理器之應用,”國立中山大學資訊工程學系研究所碩士論文, 2013.
[15] Kawaguchi, H., et al., “A Super Cut-Off CMOS (SCCMOS) Scheme for 0.5-V Supply Voltage with Picoanpere Stand-By Current,”IEEE Journal of Solid-state Circuits, vol. 35, no10, pp. 1498-1501, Oct. 2000.
[16] R.Naveen, “Low-Leakage Full Adder Circuit Using Current Comparison Based Domino Logic,”IEEE 2013.
[17] Mutoh, S., et al.,“1-V power Supply High-Speed Digital Circuit Technology with Multithreshold -Voltage CMOS,” IEEE JournalSolid-State Circuits, vol. 30, no. 8, pp. 847-854, Aug.1995.
[18] B. Guo, T. Ma, and Y. Zhang, “Design of A Novel Domino XNOR Gate for 32 nm-node CMOS Technology,”inProc. Electric Information and Control Engineering(ICEICE),15-17 Apr. 2011, pp. 289-292.
[19] C. H. Kim, K. Jae-Joon , S. Mukhopadhyay, and K. Roy , “A forward body-biased low-leakage SRAM cache: device, circuit and architecture considerations,”Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 13, pp.349-357, 2005.
[20] C. H. Kim and K. Roy, “Dynamic Vt SRAM : a leakage tolerant cache memory for low voltage microprocessors,” in Low Power Electronics and Design, 2002. ISLPED '02. Proceedings of the 2002 International Symposium on, 2002, pp.251-254.
[21] T. L. Brandon et al., “Using Stacked Bitlines and Hybrid ROM Cells to Form ROM and SRAM-ROM With Increased Storage Density,” in Circuit and Systems I: Regular Papers, IEEE Transactions on, Dec. 2006, pp.2595-2605