摘要
這篇論文中提出四個適用於嵌入式動態隨機存取記憶體的電路。首先，一個應用於字組線驅動器的高效率負電壓產生器被提出。此負電壓源產生器電路可在n-Well CMOS積體電路製程完成製作，並且有較高的輸出效率。在供應電壓源為2V時，輸出電壓可以達到-1.6V，即使供應電壓源下降至1.5V時，輸出電壓仍可達到-1.05V；相對的，傳統的負電壓產生器在2V電壓源下，輸出電壓只能達-0.67V。第二，一個適用於PMOS通道電晶體的快速字組線驅動器被提出。在2.0V供電電壓下，驅動512個記憶單元時，該字組線驅動器比傳統的字組線驅動器節省了26.8ns的時間，提高了79%的速度。第三，一個新的降低時脈振幅驅動器被提出。當供應電壓源為2.0V，操作頻率為100MHz，該驅動器配合降低時脈振幅正反器工作時，整體消耗功率比傳統的驅動器與降低時脈振幅正反器減少10%。由於上述低功率的優點，該驅動器比傳統驅動器更適用於嵌入式動態隨機存取記憶體。第四，一個修改的階層式讀出放大器電路被提出。此放大器是以新的感測放大器為基礎的階層式讀出放大器，可以以全振幅驅動輸出負載，比傳統N&PMOS交錯耦合放大器速度快了2.1ns，而且和傳統的N&PMOS交錯耦合放大器同樣具有不消耗閒置電流的優點.。上述所有電路整合在 1-Kbit embedded DRAM測試電路上供驗證。這個測試電路用2.0V供電電壓與16-Mbit的負載，結果顯示操作正確，且RAS存取時間也僅27.9ns。這顯示此四個電路技術可被應用於低電壓的高速嵌入式隨機存取記憶體。

Abstract
Four high-performance circuits design techniques for embedded DRAM are proposed. First, a negative voltage generator having high efficiency is proposed to provide the negative voltage for the modified word line driver. The negative voltage generator circuits could be manufactured in n-Well CMOS process, and its operation achieve optimal output voltage. When 2.0-V supplied voltage is applied, the output voltage of -1.6-V is obtained. Even though, the supplied voltage is scaled down to 1.5-V, the output voltage can still achieve -1.05-V. In contrast, the output voltage of traditional one under 2.0-V supplied voltage is only -0.67-V. Second, a fast wordline driver suitable for PMOS pass transistor is proposed. The wordline driver improves the turned-on time by 26.8ns compared with the traditional one and raises the operating speed by 79%. Third, a new reduced clock-swing driver is proposed. Under 2.0-V supplied voltage and 100MHz operating frequency, the total power consumption of the new driver working with RCSFF is reduced by 10% than that of traditional one working with RCSFF. For the above advantage of low power, the new driver is thus more suitable for embedded DRAM applications. Fourth, a modified hierarchical read bus amplifier is proposed. The read bus amplifier is based on the new sense-amplifier. It could drive the output by full-swing voltage. It improves the sensing speed by 2.1ns. And it got the same advantage of no dc idling current as the traditional N&PMOS cross-coupled amplifier. In this thesis, finally, the performance of these circuits is also integrated and examined in an 1-Kbit embedded DRAM test circuit. The simulation RAS access time of 27.9ns is achieved under 2.0V supplied voltage and loading of 16-Mbit embedded DRAM. This indicated the above proposed circuits could be applied in the low voltage and high speed embedded DRAM.

目錄
第一章 緒論…………………1
第二章 嵌入式動態隨機存取記憶體基本架構………3
2.1記憶單元(Memory cell)………………3
2.2 位址解碼器……………………………8
2.3字組線驅動器………………………… 8
2.4 感測放大電路(Sense Amplifier)…11
2.5 電壓源產生器(Voltage generator)11
2.6測試電路………………………………12
第三章 應用於PMOS通道電晶體之快速字組線驅動器16
3.1傳統的字組線驅動器…………………16
3.2傳統的負電壓源產生器………………18
3.3 混合式負電壓產生器…………………20
3.4 修改的負電壓產生器………………25
3.5 修改的字組線驅動器………………28
3.6 模擬結果與討論……………………31
第四章 週邊電路及感測電路………………….…34
4.1新的降低時脈振幅驅動器…………………….34
4.2 修改的階層式讀出放大電路……44
第五章 模擬結果…………………………………52
第六章結論與展望………………………………59
參考文獻…………….…………………………61

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