在深次微米積體電路中，信號傳輸延遲主要是由多層導體連線寄生電容和電阻產生。此外，由於元件縮小導致傳輸導線內的電流密度上升，使得導線內的電致遷移效應更嚴重。為了解決RC時間延遲，我們一方面使用低介電係數材料降低電容，另一方面使用銅金屬降低電阻。而銅原子擁有較高的原子量，亦能有效地抵抗電致遷移效應。由於銅金屬的硬度十分高，必須以大馬式革(Damascene)製程才能將銅填入金屬層中。又因為銅對低介電係數材料及二氧化矽有極高的擴散能力，在大馬式革製程中所使用的蝕刻終止層也需要擁有很好的抗銅能力。目前非晶系碳化矽是被認為極有潛力的材料。
在本次實驗中，我們研究以碳化矽為基底的系列化合物，觀察其組成分析，電性實驗則進行電容-電壓量測，及電流-電壓量測。另一方面，由於碳化矽薄膜有嚴重的電容-電壓延滯現象，我們嘗試分析並建立模型:(1)可移動離子(2)鐵電材料(3)載子注入(4)閘極金屬注入(5)介面鍵結電荷，它們出現在不同材料及結構中。

In the generation of deep submicron semiconductor fabrication，transmission delay is primarily caused by the parasitic resistance and capacitance (RC) in the multilevel interconnects. Besides，electromigration is also a serious issue for the reliability of devices . There are two principle methods of reducing the RC delay. The first method is to replace the Al wires with Cu interconnects which supply lower resistivity and high resistance to electromigration. The second method is to use a lower dielectric constant material as the inter-metal dielectric. But in Copper metallization，the key issue of this technology is the formation of a thin barrier layer for Cu on the surface of the SiC film to prevent the absorption of water and diffusion of Cu.
In this study，we employed films SiC base compounds to investigate their chemical bonds, I-V characteristics comparisons with Al and Cu gate. On the other hand, because of serious C-V hysteretic phenomena, we try to analyze and build up models. There five models is reasonable for our experiment: (1) mobile ions, (2) dielectric polarization, (3) carrier injection, (4) gate-electrons injection, and (5) bound charges. They happens in different materials and structures.

Contents


Acknowledgment (Chinese)…………………………………………..….2
Abstract (Chinese)………………………………………………...……..3
Abstract (English)…………………………………………………....…..4
Content…………………………………………………………………...5
Table Captions…………………………………………………………....7
Figure Captions…………………………………………………………..8


Chapter.1 Introduction
1.1 General Background……………………………….…………11
1.2 Motivation & Material Options……………………….…...…12
1.3 Thesis Organization…………………………….…………….14


Chapter.2 Intrinsic Properties of α-SiC
2.1 Introduction…………………………………..………………15
2.2 Set up instruments…………………..………………………..16
2.3 Experimental Procedure……………………..……………….17
2.4 Results and Discussion………………………………..…...…17
2.5 Summary………………………………………..………...…..18



Chapter.3 C-V Hysteretic Phenomena inα-SiC
3.1 Introduction……………………………………………..……20
3.2 Experimental Procedure………………………………..…….20
3.3 Study Results………………………………………..………..21
3.4 Possible Reasons Causing C-V Hysteretic Phenomena………22
I. Mobile ions…………………………………………………23
II. Carrier injection…………………………………………...23
III. Ferroelectric-like…………………………………………24
IV. Gate-Electrons injection………………………………….24
V. Interface bound charges…………………………………...25

3.5 Analyze Data………………………………………………….26
3.6 Summary……………………………………………………...28


Chapter.4 Conclusions and Suggestions for Future Work
4.1 Conclusions…………………………………………………..29
4.2 Future Work…………………………………………………..30


References………………………………………………………………31

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