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博碩士論文 etd-0727106-160430 詳細資訊
Title page for etd-0727106-160430
論文名稱
Title
三維繪圖中幾何運算單元之硬體設計、系統整合與驗證
Hardware Design, Integration, and Verification of Geometry Engine in 3D Graphics
系所名稱
Department
畢業學年期
Year, semester
語文別
Language
學位類別
Degree
頁數
Number of pages
127
研究生
Author
指導教授
Advisor
召集委員
Convenor
口試委員
Advisory Committee
口試日期
Date of Exam
2006-07-19
繳交日期
Date of Submission
2006-07-27
關鍵字
Keywords
三維、幾何運算
3D, Geometry
統計
Statistics
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中文摘要
近年來,電腦圖學應用越來越廣泛,尤其是三維(3D)繪圖。3D繪圖使用3-D 模型和各種影像處理產生具有三維空間真實感的影像,應用於虛擬真實情況以及多媒體的產品上,且多半是使用低成本的即時3-D電腦繪圖技術為基礎。而目前若是3-D繪圖的工作都由CPU來達成,已無法滿足今日這些交談或即時式的應用程式的需求。所以,必須利用硬體來加快處理速度,以提升整體效能。3D繪圖流程依照處理性大致分為:幾何轉換子系統(Geometry Subsystem)以及著色子系統(Render Subsystem)。而本論文主要是實做出Geometry Subsystem整體硬體,並按照OpenGL ES規格設計。其內容包含基本的座標轉換(Transformation)、光源照射(Lighting)以及刪除多餘運算的Backface Culling及Clipping,並且使用者可以設定不同的模式 (像是光源設定開關或者是三角形的輸入模式等),讓圖形產生不同效果。本論文對於3D繪圖流程提出一個新的架構,在資料每次都要經過Geometry system所需要的多個不同的運算,重新組合排列其硬體架構,達到整個硬體系統可以同步處理多的頂點。本論文按照三維繪圖處理的運算,並把相同性質的運算共用同一個硬體模組運算,提升硬體利用率,來降低硬體面積。而各個硬體模組在單獨設計時,考慮其精確度以及需求,依照目前的技術加以改進設計。而整個Geometry Subsystem硬體模組可以同步處理三個頂點值,利用控制單元以及暫存器去處理內部運算的流程。並且設計與軟體溝通的格式(包含頂點輸入值以及控制暫存器的格式),以及配合作業系統和另一個硬體Render Subsystem的需求,達成軟硬體可以整合的目標。經過層層驗證之下,可以在FPGA完成整個執行軟硬體整合的系統,並且能產生3D圖形於螢幕上。此論文的特色為結合軟硬體溝通,從軟體(Application)透過作業系統(Driver)與硬體溝通。而硬體面積以及效能等需求,都能符合規格,並且持續改善其效能。
Abstract
3D graphics pipeline can be divided into two subsystems: geometry subsystem and rendering subsystem. In this thesis, the geometry subsystem is implemented based on the specification of OpenGL ES. The major operations in the geometry subsystem are transformation, lighting, backface culling, and clipping. We propose a new architecture for the geometry subsystem that reorganizes the functions of different hardware components at three different pipeline stages so that three vertices can be processed at the same time by efficiently utilizing the hardware components. The same type of operations is executed at the same hardware component but maybe in different pipeline stages in order to increase the hardware utilization efficiency and to reduce the overall area cost. We also improve the designs of individual hardware components proposed in previous paper so that the area cost can be reduced while still meeting the operation accuracy. The interfaces and communication registers among the hardware geometry subsystem, another hardware rendering subsystem and OS drivers are also designed so that the complete OpenGL API software programs can be executed in the integrated 3D graphics system. In addition to the traditional RTL verification, the complete system is also mapped to a FPGA board to demonstrate the rendered 3D graphics pictures on the screen. Thus, the complete hardware/software integration (including OpenGL API application software, OS drivers, and graphics hardware) is verified.
目次 Table of Contents
CHAPTER 1 概論 2
1.1 本文大綱 2
1.2 研究動機 2
CHAPTER 2 研究背景與相關研究 3
2.1 研究背景:三維(3D)圖學簡介及應用 3
2.2 Geometry System所需運算 9
2.2.1 Geometry System 介紹 9
2.2.2 座標運算(transformation) 16
2.2.3 顏色運算(Lighting) 26
2.2.4 Culling & Clipping 30
2.3 相關研究 32
2.3.1 三維(3D)硬體化相關設計 32
CHAPTER 3 Geometry System實作 36
3.1 Geometry System硬體設計流程 36
3.1.1 Pipeline 36
3.1.2 效能評估及架構分析 40
3.1.3 硬體架構 48
3.2 Geometry System硬體單元 55
3.2.1 Four Madd (矩陣相乘) 55
3.2.2 Truncated Multiplier 58
3.2.3 Normalization (正規化) 64
3.2.4 Exponentiation Unit(指數運算) 68
3.2.5 Reciprocal (倒數) 74
3.2.6 Culling 76
3.2.7 Pre_Clipping 78
CHAPTER 4
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