隨著可攜式電子產品和通訊儀器的快速發展，都趨向於輕、薄、短、小的特性發展，所以電子封裝也朝著這方向而努力發展，而晶圓級封裝(WLCSP)因為輕薄短小的特性已經廣泛的應用在可攜式電子產品上，預估其將在未來成為主流趨勢，卻因可攜式電子產品可以隨身攜帶或移動，造成其破壞失效的狀況發生可能多到不計其數，而且其使用環境也不盡然一樣，但大多可歸咎於錫球接點很容易在動態負荷下產生損壞，進而造成電子元件無法正常運作，所以對封裝體進行反覆負載的研究愈來愈受重視。
本文對晶圓級封裝體結構分為鈍化層(Passivation)、重新佈線層(RDL)、凸塊底層金屬(UBM)等參數，將各組不同晶圓級封裝體進行三種可靠度試驗，分別為掉落衝擊試驗、彎曲循環試驗、溫度循環試驗，並以韋伯分佈表示晶圓級封裝體的特徵壽命，觀察結構對其壽命週期之影響，另外以紅染料試驗分析失效錫球之分佈位置並推測最早失效錫球可能出現之地方，也使用掃描式電子顯微鏡觀察錫球或晶圓級封裝體上裂縫出現之位置，推論裂縫可能之路徑。
三種實驗互相比較之後，以掉落衝擊實驗觀察到晶圓級封裝體結構與特徵壽命有明顯關係，以往掉落衝擊常會造成錫球介金屬(IMC)產生裂縫，而晶圓級封裝體結構則觀察到其裂縫轉變為第二層鈍化層與凸塊底層金屬界面之角落。三種實驗後之晶圓級封裝體失效錫球位置一致性地分佈於封裝體之角落。溫度循環實驗之失效錫球在掃描式電子顯微鏡下，觀察到不同組之失效錫球有著類似相同之失效機制，其裂縫橫切過錫球，位置在錫球體上靠近封裝體側。

The Wafer Level Chip Scale Package (WLCSP) is gaining popularity for its performance and ability to meet the miniaturization requirements of portable consumer electronics, such as cell phones. For the industry of electronic package, the package life of electronic products is deemed as the essential consideration in the operation period. In practice, electronic products are usually damaged due to a harsh mechanical impact, such as drop and bending. The solder interconnections provide not only the electronic path between electric components and printing circuit board, but also the mechanical support of components on the printing circuit board, so that the reliability of solder interconnection becomes an essential consideration for a package.
In the thesis several parameters, including redistribution layer (RDL) material and thickness, passivation material and thickness, under-bump metallization (UBM) structure factors are discussed. A variety of WLCSP structures are investigated for solder joint reliability performance. In addition to the fatigue lives of the test vehicle, locations and modes of fractured solder joints were observed.
It was found that wafer level packaging structure under drop clearly related with the characteristic life. The weakest point of solder ball was intermetallic compound (IMC), and wafer level packaging structure was the crack into the second passivation layer and UBM interface of the corner. WLCSP under temperature cycling test was done and observed the fracture only occurred at the solder ball near the package.

摘要i
Abstract ii
目錄iii
圖目錄vi
表目錄x
第一章 緒論1
1-1前言1
1-2封裝簡介2
1-3文獻回顧4
1-4組織與章節6
第二章 晶圓級封裝與可靠度簡介7
2-1晶圓級封裝簡介7
2-1-1晶圓級封裝7
2-1-2晶圓級封裝重新佈線與凸塊成形過程8
2-1-3晶圓級封裝之組裝 9
2-2可靠度分析9
2-2-1韋伯分佈10
2-2-2韋伯分佈的物理涵義12
第三章 實驗工作16
3-1實驗規劃16
3-2表面黏著技術16
3-2-1設備介紹16
3-2-2表面黏著技術之流程簡介17
3-3實驗試片18
3-3-1實驗封裝體介紹18
3-3-2實驗印刷電路板介紹18
3-4掉落衝擊實驗19
3-4-1實驗說明19
3-4-2掉落衝擊儀器設備 19
3-4-3掉落衝擊實驗規範 20
3-4-4掉落衝擊實驗步驟 22
3-5彎曲循環實驗22
3-5-1實驗說明22
3-5-2彎曲循環儀器設備 23
3-5-3彎曲循環實驗規範 23
3-5-4彎曲循環實驗步驟 24
3-6溫度循環實驗25
3-6-1實驗說明25
3-6-2溫度循環儀器設備 25
3-6-3溫度循環實驗規範 25
3-6-4溫度循環實驗過程 26
3-7實驗後試片分析與觀察26
3-7-1實驗結果分析說明 26
3-7-2實驗結果分析設備介紹27
3-7-3實驗結果分析步驟說明27
3-7-4失效模式定義28
第四章 實驗結果與討論 39
4-1掉落衝擊實驗39
4-1-1失效週期統計39
4-1-2韋伯分佈39
4-1-3錫球失效模式分佈 41
4-1-4掃瞄式電子顯微鏡觀察分析42
4-2彎曲循環實驗45
4-2-1失效週期統計45
4-2-2韋伯分佈45
4-2-3錫球失效模式分佈 46
4-2-4掃瞄式電子顯微鏡觀察分析47
4-3溫度循環實驗47
4-3-1失效週期統計48
4-3-2韋伯分佈48
4-3-3錫球失效模式分佈 49
4-3-4掃瞄式電子顯微鏡觀察分析50
第五章 結論與未來展望 95
5-1結論95
5-2未來展望96
參考文獻97

[1]J.W. Jang, J.K. Lin, and D.R. Frear, “Failure Morphology after the Drop Impact Test of the Ball Grid Array Package with Lead-Free Sn-3.8Ag-0.7Cu on Cu and Ni Under-Bump Metallurgies,“ Journal of Electronic Materials, Vol. 36, No. 3, 2007.
[2]E.H. Wong, S.K.W. Seah , W.D. van Driel, J.F.J.M. Caers, N. Owens , Y.-S. Lai, “Advances in the drop-impact reliability of solder joints for mobile applications,” Microelectronics Reliability, Vol. 49, 2009, pp. 139-149.
[3]Frank Kao, Zhi Hao Tseng, Chun Sheng Ho, Stan Chen, Chang-Yi Lan, Feng Lung Chien, “A Study of Board Level Reliability Test with Bump Structure of WLCSP Lead-Free Solder Joints”, Assembly and Circuits Technology, 2007.
[4]Tong Yan Tee, Long Bin Tan, Rex Anderson, Hun Shen Ng, Jim Hee Low, Choong Peng Khoo, Robert Moody, Boyd Rogers, “Advanced Analysis of WLCSP Copper Interconnect Reliability under Board Level Drop Test”, 10th Electronics Packaging Technology Conference, 2008.
[5]Yuan Lin Tzeng, Eason Chen, Jeng Yuan Lai, Yu Po Wang and C.S. Hsiao, “WLCSP Parameter Study for Ball Reliability Analysis”, Electronic Components and Technology Conference, 2009.
[6]Dave Reiff, Edwin Bradley, “A Novel Mechanical Shock Test Method to Evaluate Lead-Free BGA Solder Joint Reliability,” Electronics Packaging Technology Conference, 2005.
[7]蔡翰輝，“晶圓級封裝在循環彎曲負載測試下之可靠度分析”，國立中山大學機械與機電工程研究所碩士論文，2004。
[8]Yi-Shao Lai, Tong Hong Wang, Han-Hui Tsai, Ming-Hwa R. Jen, “Cyclic bending reliability of wafer-level chip-scale packages,” Microelectronics Reliability, Vol. 47, 2007, pp. 111-117.
[9]Chi-Ko yu, Graver Chang, Tina Shao, Cherie Chen, Jeffrey Lee, Jenn-Ming Song, Yao-Ren Liu, Mon-Chin Tsae, “Failure Mode Evolution of WLCSP on Board by Dynamic Bend Method,” Assembly and Circuits Technology Conference, 2009.
[10]X.J. Fan, B. Varia, Q. Han, “Design and optimization of thermo-mechanical reliability in wafer level packaging ,” Microelectronics Reliability, Vol. 50, 2010, pp. 536-546
[11]“Subassembly Mechanical Shock”, JESD22-B110, JEDEC Solid State Technology Association, March 2001.
[12]“Board Level Drop Test Method of Components for Handheld Electronic Products”, JESD22-B111, JEDEC Solid State Technology Association, July 2003.
[13]“Board Level Cyclic Bend Test Method for Interconnect Reliability Characterization of Components for Handheld Electronic Products”, JESD22B113, JEDEC Solid State Technology Association, March 2006.
[14]“Temperature Cycling”, JESD22-A104-B, JEDEC Solid State Technology Association, July 2000.
[15]許修豪，“在熱循環下晶圓級晶片尺寸封裝可靠度分析”，國立成功大學工程科學研究所碩士論文，2002。
[16]蔡俊弘，“晶圓級封裝體於落下試驗之田口法最佳化分析”，國立高雄大學電機工程學系研究所碩士論文，2010。
[17]田民波，“半導體電子元件封裝技術”，五南圖書出版書局，2005。
[18]陳耀茂，“可靠度工程-方法與應用”，五南圖書出版書局，2001。
[19]蔡宗岳，“晶圓級封裝承受JEDEC上板級掉落衝擊測試之研究”，國立成功大學工程科學系博士論文，2008。
[20]Umesh Sharma, Ph.D., Harry Gee, and Phil Holland, “Reliability Comparison of Aluminum Redistribution based WLCSP Designs,” Microelectronics and Packaging Conference, 2009.
[21]劉昌明，電訊接點配置、幾何及製造參數對微電子元件可靠度影響之研究，國立清華大學動力機械工程學系博士論文，2004。
[22]江國寧，“微電子系統封裝基礎理論與應用技術”，滄海書局，2006。
[23]Xuejun Fan, Qiang Han, “Design and Reliability in Wafer Level Packaging,” 10th Electronics Packaging Technology Conference, 2008.
[24]Deok-Hoon Kim, Peter Elenius, Michael Johnson, Scott Barrett, “Solder joint reliability of a polymer reinforced wafer level package,” Microelectronics Reliability, Vol. 42, 2002, pp. 1837-1848.