本論文提出一個基於3D IC堆疊階段的嶄新測試架構，名為可適性測試模組(Scalable Test Module, STM)。STM將以晶粒的型態與待測晶粒(die under test)一同整合，藉以解決3D IC之測試存取問題並降低測試成本。STM以面積相對於IEEE 1500標準較小的IEEE 1149.1 (JTAG)測試標準進行開發，待測晶粒僅需包覆JTAG包裝界面即可以隨插即用方式與STM進行整合，進行測試存取及應用。STM本身可產生所有所需測試控制訊號，並可擷取並比對測試結果、支援平行測試、及廣播測試資料以改善JTAG存取較慢的缺點。STM更可互相連接，一同運作使更多待測晶粒可同時測試，以更加提升測試效率。使用者可根據待測晶粒之數量與種類、測試硬體成本與測試時間等因素彈性調整STM晶粒的數量，以取得一個平衡之測試解決方案。

本論文所提出之STM的初始版本已利用TSMC T18製程實現後下線於103A梯次，並且完成晶片的測量。初始版本於合成階段的最高操作頻率為140MHz，合成面積為27387um2(約為2739個基本邏輯閘)；於佈局階段的最高操作頻率為125MHz，佈局面積為392329 um2。最佳化版本亦已利用TSMC T18製程實現，合成階段的最高操作頻率為140MHz，合成面積為27573um2(約為2758個基本邏輯閘)；於佈局階段的最高操作頻率為125MHz，佈局面積為390340 um2。使用ISCAS C7552及S38584 標準電路及IWLS DMA標準電路的分析結果也展示了STM測試效率可藉由更改STM之數量彈性調整之特性。

This thesis presents a new test architecture based on 3D IC stacking stage, called scalable test module (STM). STM will be fabricated a separate die and integrated with dies unde test (DUT) to address the test access problem of 3D IC with low test cost. STM is developed based on the IEEE 1149.1 (JTAG) test wrapper that has lower hardware overhead compared with the IEEE 1500 Std. DUTs only need to be wrapped by JTAG wrappers and then can be integrated with STM in a plug-and-play manner to perform test access and test application. STM can generate all the required test control signals on-die, and also can retrieve and compare test responses, support parallel testing and broadcast test data to address the possible long test time issue for JTAG. Furthermore, multiple STMs can be connected together and work collaboratively to make more DUTs be tested concurrently for further increasing the test efficiency. Users can flexibly adjust the total number of integrated STMs to achieve a good trade-off between test time and test cost.

The prelimanary version of the proposed STM has been fabricated by using the TSMC T18 process and tested by Advantest 93K ATE. The logic synthesis results show that the maximum operation frequency is 140MHz, and the cell area is 27387um2 (2739 basic logic gates). After the physical design stage, the maximum operating frequency is 125MHz, and the layout area is 392329 um2. We also implement an optimized version of STM and implement it using the TSMC T18 process. The maximum operating frequency is 140 (125) MHz, and the area is 27573um2 (390340 um2) after the logic synthesis (physical design) process. The analysis results using the ISCAS C7552及S38584 and IWLS DMA benchmark circuits demonstrate the scalability of STM for enhancing the test efficiency.

論文審定書 ii
誌謝 iii
中文摘要 iv
英文摘要 v
目錄 vi
圖目錄 viii
表目錄 xii
第一章 簡介 1
1.1 3D IC簡述 1
1.2 3D IC測試流程 1
1.3 本論文之貢獻 3
1.4 論文大綱 3
第二章 IEEE 1149.1測試標準包裝 4
第三章 可適性測試模組之介紹 10
3.1 基於3D IC測試的嶄新測試架構 10
3.2 可適性測試模組之測試運作流程 15
3.2.1 初始化 15
3.2.2 下載Test Data 16
3.2.3 執行測試存取 18
3.2.4 上傳測試結果 23
3.3 可適性測試模組之硬體架構 24
3.3.1 Download區塊 25
3.3.2 Test Access Mechanism(TAM)區塊 26
3.3.3 Upload區塊 27
3.3.4 Storage區塊 28
3.4 可適性測試模組之硬體實現 30
 
第四章 模擬結果 33
4.1 初始化 33
4.1.1 設定Level Index 33
4.1.2 下載Upload Type 33
4.2 下載測試資料 34
4.2.1 下載Receive Signal 34
4.2.2 下載Mission 35
4.2.3 下載PD1 35
4.2.4 下載PD2 36
4.2.5 下載RD1 37
4.2.6 下載RD2 38
4.3 執行測試存取 40
4.3.1 初始化JTAG 40
4.3.2 解碼Test Data 41
4.3.3 設定JTAG Instruction 41
4.3.4 執行Capture & Shift DR 43
4.3.5 執行Shift DR Only 45
4.3.6 比對TDO訊號 46
4.3.6 模擬DUT有fault的情況 47
4.3.7 結束測試存取 48
4.4 上傳測試結果 50
4.4.1 初始化 50
4.4.2 上傳測試結果 50
第五章 測試時間分析 53
5.1 各個運作流程的執行時間 53
5.2 Internal Test範例之時間分析 55
5.3 Internal Test於一般化情況之時間分析 58
5.4 實際電路執行Internal Test之時間 65
5.5 External Test之時間分析 67
 
第六章 結論與成果 69
參考文獻 70

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