Title page for etd-0728104-232310


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URN etd-0728104-232310
Author Chih Ming
Author's Email Address m9139622@student.nsysu.edu.tw
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Department Electrical Engineering
Year 2003
Semester 2
Degree Master
Type of Document
Language zh-TW.Big5 Chinese
Title A Nano MOSFET with Spacer-like Silicide Source/Drain and Halo Implantation
Date of Defense 2004-06-30
Page Count 56
Keyword
  • depletion
  • memory
  • extension
  • silicide
  • Abstract In deep submicron region, scaling the sizes of devices and chips down is indispensable. The silicide at ultra-shallow extension area is used in order to keep low sheet resistance while junction depth is scaled. To  introduce the implant between source and channel keeps high saturation current. Furthermore, we put two blocks of oxide between source and channel to suppress the short channel effect, which are able to resist depletions. We also demonstrate the capacitor-less memory cell. We use the variation of the charge and bias replacing the real capacitor. The device is promising candidate for reduced chip size.
    According to the simulation results of ISE TCAD, the device with silicide at ultra-shallow extension area and the implantation between source and channel provide higher saturation current. The MOS with block oxide has high Ion/Ioff  and low DIBL. We simulate different materials, different high and width of the block oxide, and discuss the effects of those device’ characteristics. We show two methods of the implantation which can improve the charge density of pseudo neutral region. Those three structures provide an solution to make device and chip be scaled down easily.
    Advisory Committee
  • Shyh Jye Joe - chair
  • Yao Tsung Tsai - co-chair
  • Chia Hsiung Kao - co-chair
  • Jyi Tsong Lin - advisor
  • Files
  • etd-0728104-232310.pdf
  • indicate not accessible
    Date of Submission 2004-07-28

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