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博碩士論文 etd-0728104-232310 詳細資訊
Title page for etd-0728104-232310
論文名稱
Title
含類似邊襯之金屬矽化物源/汲極和光圈摻雜之金氧半場效電晶體
A Nano MOSFET with Spacer-like Silicide Source/Drain and Halo Implantation
系所名稱
Department
畢業學年期
Year, semester
語文別
Language
學位類別
Degree
頁數
Number of pages
56
研究生
Author
指導教授
Advisor
召集委員
Convenor
口試委員
Advisory Committee
口試日期
Date of Exam
2004-06-30
繳交日期
Date of Submission
2004-07-28
關鍵字
Keywords
記憶體、延伸區、金屬矽化物、空乏區
depletion, memory, extension, silicide
統計
Statistics
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中文摘要
進入深次微米時代,元件及晶片面積縮小是必然的趨勢。元件需要有夠淺的接面防止punch through及夠低的電阻來提高電流。縮小元件所造成的短通道效應也是要克服的。我們提出用金屬矽化物和摻雜的方式來達成淺接面,並提高飽和電流。另外對於縮小元件造成的短通道效應,在源極/汲級之間置入兩塊絕緣的材料(block oxide),來阻隔空乏區的電場。在減低晶片面積的部份,對於要求集積度高的記憶體,則提出不需要外部電容的方式,以元件本身內部電荷變化,和所施加的偏壓變化來替代電容,降低晶片面積,簡化製程的步驟。
依據ISE TCAD模擬發現,金屬矽化物和摻雜的方式能有效地提高飽和電流。而採用block oxide的元件能增加Ion/Ioff,降低DIBL。同時也探討不同block oxide的高度、寬度及材料對元件特性的影響。對於單電晶體的記憶體,採用兩種不同的摻雜以加更多的電荷密度。這三種架構使得元件縮小變的更直接也更容易,能符合未來元件製作的趨勢。
Abstract
In deep submicron region, scaling the sizes of devices and chips down is indispensable. The silicide at ultra-shallow extension area is used in order to keep low sheet resistance while junction depth is scaled. To introduce the implant between source and channel keeps high saturation current. Furthermore, we put two blocks of oxide between source and channel to suppress the short channel effect, which are able to resist depletions. We also demonstrate the capacitor-less memory cell. We use the variation of the charge and bias replacing the real capacitor. The device is promising candidate for reduced chip size.
According to the simulation results of ISE TCAD, the device with silicide at ultra-shallow extension area and the implantation between source and channel provide higher saturation current. The MOS with block oxide has high Ion/Ioff and low DIBL. We simulate different materials, different high and width of the block oxide, and discuss the effects of those device’ characteristics. We show two methods of the implantation which can improve the charge density of pseudo neutral region. Those three structures provide an solution to make device and chip be scaled down easily.
目次 Table of Contents
第一章、導論.............................................1
1-1、金屬矽化物替代延伸區…………………………………………1
1-2、單電晶體記憶……………………………………………………3
1-3、抑制延伸區的架構………………………………………………5
第二章、新元件結構的模擬...……………………………….......7
2-1、金屬矽化物延伸區的模擬……………………….………………7
2-2、單電晶體記憶體的模擬………………………………….………9
2-3、抑制短通道效應新結構的模擬…………………..……………21
第三章、新元件結構的製作…………………….………….…….36
3-1、金屬矽化物延伸區的實作…………………………….………36
3-2、單電晶體記憶體的實作…………………………………………38
3-3、抑制短通道效應新結構的實作………………………..………42
3-4、實作結果與討論…………………………………….…………43
第四章、結論與未來發展……………………………………..46
4-1、結論……………………………………………………………..46
4-2、未來發展………………………………………………………..46
參考文獻……………………………………………….……..48
參考文獻 References
[1] D. A.Neamen, “Semiconductor Physics & Device, second Edition”, Mc Grill Hill July 2001 p.539~566
[2] K. Ikeda, Y. Yamashita, A. Endoh, T. Fukano, K. Hikosaka, and T.Mimura “50-nm Gate Schottky Source/Drain p-MOSFETs With a SiGe Channel”IEEE ELECTRON DEVICE LETTER,VOL.23,NO.11,NOVEMBER 2002
[3] J. Guo and M. S. Lundstrom “A Computational Study of Thin-Body, Double-Gate, Schootky Barrier MOSFETs ” IEEE TRANSACTIONS ON ELECTRON DEVICE LETTER, VOL.49, NO.11, NOVEMBER 2002
[4] X. Liu, K. Luo, G. Du, L. Sun, J. Kang, R. Han“N Channel SOI Schottky Barrier Transister” Solid-State and Integrated-Circuit Technology, 2001. Proceedings.
[5] J. Kedzierski, P. Xuan, E. H. Anderson, J. Bokor, C. Hu "Complementary silicide source/drain thin-body MOSFETs for the 20 nm gate length regime" IEDM Technical Digest. International , 10-13 Dec. 2000
[6] H. C. Lin, C. Y. Lu, M.F. Wang ,and T. Y. Huang“ Ambipolar Schottky Barrier SOI MOSFETs” Semiconductor Device Research Symposium, 2001 International , 5-7 Dec. 2001
[7] C. Wang, Snyder, J. P., Tucker, J. R. “Sub-50-nm PtSi Schottky source/drain p-MOSFETs” Device Research Conference Digest, 1998. 56th Annual , 22-24 June 1998
[8] W. M. Chung, C. F. Cheng, M.C. Poon, C.W. Kok, M. Chan “Amorphous Silicon Deposition Temperature Optimization on Advanced Polysilicon Thin-Film Formation Using Metal-Induced Lateral Crystallization Technology" Electron Devices Meeting, 2002 IEEE Hong Kong , 22 June 2002
[9] C. Yin, Philip C.H. Chan, Victor W.C. Chan“Raised S/DGate-All-Around CMOS Using MILC”2002 IEEE International SOI conference,10/2
[10] L. A. Zheng, E. Ping“Metal-insulator-Si (MIS)structure for advanced DRAM cell capacitor” Microelectronics and Electron Devices, 2004 IEEE Workshop on , 16
[11] S. Yoon, O. Kwon, S. Yoon, T. Won “An extractingcapacitance in a stacked DRAM cell by numerical method” Simulationof Semiconductor Processes and Devices, 2000. SISPAD 2000. 2000International Conference on , 6-8 Sept. 2000
[12] Y. Park, K. Kim “COB stack DRAM cell technology beyond 100nm technology nod”, IEDM Technical Digest, 2-5 Dec. 2001

[13] S.Okhonin, M. Nagoga, Sallese, J. M. Fazan, P “A SOI capacitor-less 1T-DRAM concept” SOI Conference, 2001 IEEE International , 1-4 Oct. 2001
[14]J. Guo, Lundstrom , M. S. “A computational study of thin-body, double-gate, Schottky barrier MOSFETs” Electron Devices, IEEE Transactions on , Volume: 49 , Issue: 11 , Nov. 2002
[15]N. K., Wada, S. K., Saito, S., Ishihama, A. “Suppression of MOSFET reverse short channel effect by channel doping through gate electrode” Semiconductor Manufacturing Symposium, 2001 IEEE International , 8-10 Oct. 2001
[16] X.HONG “introduction to semiconductor manufacture technology”2003
[17]P. J., M. S., Cristoloveanu, S., Skotnicki, T. “Silicon-on-nothing MOSFETs: performance, short-channel effects, and backgate coupling” Electron Devices, IEEE Transactions on , Volume: 51 , Issue: 2 , Feb. 2004
[18]張勁燕 “深次微米製程技術”五南書局p180,186 2002
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