在無線通訊系統中，傳送端經常使用迴旋碼將所要傳送的資料進行編碼。而接收端所使用的解迴旋碼機制中，維特比演算法(Viterbi Algorithm)是較為出色的一種方法。為了能在行動通訊的裝置上更有效率地使用這種演算法，因此發展出維特比解碼器。例如在2G及3G的行動電話上，經常使用此種解碼器做為基地台與手機端之間無線通訊的解碼機制。但是維特比解碼器(Viterbi Decoder)在2G行動電話上，大約佔整體訊號接受器三分之一的功率消耗。因此，在手機系統上，如何減少維特比解碼器的功率消耗，成了非常重要的設計考量。
維特比解碼器在存活記憶體單元中使用大量的暫存器，其原因是要讓解碼器在接收到足夠長度的迴旋碼之後，可以出現自然收斂的情形，但是這將使得存活記憶體單元消耗大量功率。本論文的目標，主要在減少存活記憶體單元的功率消耗，我們使用累積路徑計量值比較單元(Path Metric Compare Unit)，找出最佳路徑值的狀態，因此可使存活記憶體單元減少一半數量的暫存器與多工器，大幅降低整體解碼器面積以及功率消耗。
此外，本論文中我們也結合了額外的錯誤偵測電路，在接收到的迴旋碼進入維特比解碼器之前，先將迴旋編碼中出現雜訊干擾的區段給標記出來。若某迴旋碼區段受雜訊影響，則該區段將進入維特比解碼器之中進行解碼，反之則進入低功率的解碼器，並且將維特比解碼器中此區段的存活記憶體單元以閘控時脈(clock Gating)的機制加以關閉，以減少存活記憶體單元內不必要的功率消耗。
實驗結果顯示，本論文提出之適應性維特比解碼器會因為雜訊影響的嚴重程度不同，而使整體功率消耗隨之變動。在高雜訊時，較傳統維特比解碼器省約21%之功率消耗。在低雜訊時，則比傳統解碼器省約44%之功率消耗。因此，我們提出的方法確實可以成功讓解碼器達到低功率的功\效。

In wireless communication system, convolutional coding method is often used to encode the data. In decoding convolutional code (CC), Viterbi algorithm is considered to be the best mechanism. Viterbi decoder (VD) was developed to execute the algorithm on mobile devices more effectively. This decoder is often used on 2G and 3G mobile phones. However, on 2G phones, VD consumes about one third of total power consumption of the signal receiver. Therefore it is very necessary to reduce the power consumption of VD on 2G and 3G phones.
VD uses large amount of register in survivor metric unit (SMU), so that the decoder can receive enough CC and converge automatically. The goal of this thesis is to decrease power consumption of SMU by using path metric compare unit (PMCU) to find the best state of path metric unit (PMU). This way decreases half of registers and multiplexers required in SMU, leading to significant area reduction in decoder. During the process of signal transmission in wireless communication, different causes like the atmosphere, outer space radiation and man-made will interfere the signal by different degree. The stronger the noise is, the more interference CC will get.
The error detection circuit used will mark the sections with noise interference before the CC enters the VD. If CC is interfered, it will be decoded by the whole VD. Otherwise, it will be decoded by low power decoder, where the controller will start clock gating mechanism on SMU to close up unnecessary power consumption block.
The power consumption of is varying proposed Adaptive Viterbi decoder according to the interference degree. When interference degree is high, the power consumption is 21% less than conventional VD; when interference is low, it is 44% less. The results show that the proposed method can effectively reduce the power consumption of VD.

目　　錄
頁數
誌謝..............................................................................................................................Ⅰ
中文摘要......................................................................................................................Ⅱ
英文摘要......................................................................................................................Ⅲ
目 錄..........................................................................................................................Ⅴ
表　次..........................................................................................................................Ⅶ
圖　次..........................................................................................................................Ⅷ

第一章 緒論................................................................................................................1
1.1 研究背景.......................................................................................................1
1.2 研究動機與方法...........................................................................................2
1.3 論文章節編排...............................................................................................3

第二章 維特比演算法之背景知識............................................................................5
2.1.1 迴旋碼簡介....................................................................................................5
2.1.2 迴旋碼編碼範例............................................................................................6
2.2.1 維特比演算法簡介........................................................................................7
2.2.2 維特比演算法解碼範例..............................................................................10
2.3 暫存器交換法.............................................................................................12
2.4 追溯法.........................................................................................................14
2.5 軟式決策.....................................................................................................16
2.6.1 迴旋碼之錯誤偵測概念..............................................................................18
2.6.2 迴旋碼之錯誤偵測範例..............................................................................21

第三章 區段雜訊辨識與截斷長度縮短..................................................................22
3.1 截斷長度之縮短法.....................................................................................22
3.2 雜訊干擾之區段判定.................................................................................24
3.3 ISPMC判定.................................................................................................26

第四章 硬體架構......................................................................................................30
4.1 傳統維特比解碼器之硬體架構.................................................................30
4.2 加-比較-選擇單元正規化..........................................................................33
4.3.1 適應性維特比解碼器架構..........................................................................36
4.3.2 區段錯誤辨識之維特比解碼器..................................................................39
4.4 累積路徑計量值比較單元.........................................................................42

第五章 硬體驗證與實驗數據..................................................................................44
5.1 軟體模擬雜訊通道.....................................................................................44
5.2 矽智產驗證.................................................................................................45
5.3 硬體規格.....................................................................................................46
5.4 實驗數據.....................................................................................................47

第六章 結論與未來工作..........................................................................................51

參考文獻 ..................................................................................................................52

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