由於現代製程的快速進步，許多系統晶片(SoC:System-on-Chip) 為了要滿足不同的程式
執行，其快取記憶體的容量也隨之增大。快取記憶體在整個系統晶片中扮演非常重要
的角色，其所占整個晶片60%的面積也是不可小覷。但並不是每個使用者所開啟的應
用程式都會使用上所有的快取記憶體空間，這導致尚未被使用到的空間變成一種浪
費，不僅僅是空間上的浪費，也是能源上的浪費。因此，在工業界中發展了可變動快
取記憶體大小的技術。近年來，草稿記憶體(SPM:Scratchpad Memory)將這些變動快取
記憶體中被關掉的部份進而擴充成可使用的額外記憶體空間，SPM可以使效能增進或
是加速指令的傳送。儘管如此，在使用SPM之時，僅有data RAM被使用到而tag RAM
則是閒置的。在這篇論文中，提出一個架構可將這些被當作SPM時被閒置的tag RAM空
間加以回收利用。這篇論文將此架構實作於與ARM兼容的CPU並進行實驗。實驗主要
是使用相對應ARM Cortex-A5 CPU的快取記憶體大小，4KB，4way，可存放8個word。
應用此架構雖然額外多了0.08%的硬體，但是卻可以回收12.5%的記憶體空間。

In almost every typical SoCs (System-on-Chip) in modern days, the size of cache grows larger
as new SoC fabrics enhanced to satisfy the variety of workloads. Cache occupies the whole
chip area more than 60% in SoC. Most of the time, application does not use the entire cache
space. Consequently, the underutilized cache space consume a certain power constantly without
any contribution. Thus, some of the industry company in present day, starting to develop
mechanisms to make the cache size reconfigurable. In recent work, an idea of scratchpad memory
extends the turned-off part of cache space as local memory, also called SPM (scratchpad
memory), which can benefit other activities to further increase the performance or enhance instruction
delivery. However, SPM only uses the part of data RAMs, the tag RAMs part is still
remaining un-used. In this work, we proposed an architecture that can exploit the SPM space
by reusing tag RAMs in either instruction or data cache. Implementing the proposed architecture
on an ARM compatible CPU data cache for case study. The experiment results show that
we can reclaim 12.5% of memory space with 0.08% hardware overhead in the configuration of
4KB, 4 way-associative cache with 32 byte line size which is equivalent to ARM Cortex-A5.

論文審定書 + i
Acknowledgments + iii
摘要 + iv
Abstract + v
List of Figures + ix
List of Tables + x
List of Listings + xi
Chapter 1 Introduction + 1
1.1 Background + 1
1.2 Motivation + 2
1.3 Organization of the Thesis + 4
Chapter 2 Related Works + 5
2.1 Reconfigurable Cache + 6
2.1.1 Data SPM + 6
2.1.2 Tag RAMs Reuse + 6
2.2 Performance Improvement Using Tag RAMs + 7
2.2.1 Energy Saving + 7
2.2.2 System Reliability + 8
2.3 AdditionalFunction + 10
2.3.1 Tag-BasedReplacement + 10
2.3.2 Look up table + 10
2.3.3 Trace Cache + 10
2.4 Application of SPM and Cache Miss Rate with SPM + 10
2.5 Discussions + 13
Chapter 3 The Tag SPM Architecture + 14
3.1 Assumption + 14
3.2 Tag SPM Architecture Overview + 15
3.3 Addressing Method + 17
3.4 Cache Operation + 18
3.5 Data/Tag SPM Controller & Operations + 18
Chapter 4 Tag Width Solution + 21
4.1 2-Cycle-Access Tag SPM + 21
4.1.1 Normal Cache Operation for 2-Cycle-Access + 23
4.1.2 Tag SPM Operation for 2-Cycle-Access + 23
4.2 2B/W Tag SPM + 23
4.2.1 Normal Cache Operation for 2B/W + 25
4.2.2 Tag SPM Operation for 2B/W + 26
4.3 Summary + 27
Chapter 5 Experimental Result + 28
5.1 Experiment Environment + 28
5.2 Hardware Gate Count + 29
5.3 Critical Path + 30
5.4 Analysis of Tag RAMs Space with Tag SPM + 30
Chapter 6 Conclusion + 33
Chapter 7 Future Works + 34
Bibliography + 35
Appendix A Tag SPM Test Pattern + 37

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