隨著製程與軟體科學快速的進步，嵌入式系統也日益複雜，對於產品上市的時間要求
也越來越短，因此對於要整合一個完整的系統晶片(SoC)，如何在整合時有效且快速地
找出問題，便也成為一個重要的議題。
本論文提出一整合軟硬提除錯之方法，利用原本微理器內建之嵌入式電路仿
真器(Embedded In-Circuit Emulator)配合元件與Wrapper間加入Wrapper-Base電路仿真
器(Wrapper-Base In-Circuit Emulator)，藉此裝置抓取原件到Wrapper之間之傳輸資料，
配合除錯介面軟體，將抓取出來的訊號抽象化，並與軟體在於同一介面顯示，同時也
參考現行軟體除錯常見之行為與指令，設計對應之硬體指令與行為，使設計者可以從
同一個介面上同時控制軟硬體，並同時顯示軟硬體之除錯資訊，讓硬體除錯像軟體除
錯般簡單，而使使用者可使更快找到嵌入式系統之錯誤，減少整合需要的時間，加速
整體之設計。

With the increasing of manufacture and software design technology, embedded system now
become more and more complex, time-to-market also become more short. For integrated a
system-on-chip (SoC), how to debug the errors while integrate become a important problem.
This thesis proposed a method that integrate both software and hardware debugging. To catch
the HW transaction information by using the embedded in-circuit emulator(EICE) in micropro-
cessors and the proposed wrapper-base in-circuit emulator(WBICE) between IP and wrapper.
Abstract the signals trace from HW and display both SW and HW debug information in the
same degubber. Reference to SW debug actions and command to design HW debug actions
and commands, make user can control and debug both SW and HW in the same interface. Let
HW debugging like SW debugging. Reduce the integration time and time-to-market.

Contents
論 文 審 定 書+i
Acknowledgments+iii
摘 要+v
Abstract+vi
List of Figures+x
List of Tables+xii
Chapter 1 Introduction+1
1.1 Background+1
1.2 Motivation+2
1.3 Contributions of the Thesis+3
1.4 Organization of the Thesis+3
Chapter 2 Related Works+4
2.1 My Research Tree+4
2.2 Software Debugger+5
2.2.1 GNU Debugger+5
2.2.2 Open On-Chip Debugger+6
2.3 Wrapper-base ICE Design+7
2.3.1 Memory Interface Protocol+7
2.3.1.1 Open Core Protocol(OCP)+8
2.3.1.2 Generic Interface Protcol+10
2.3.2 Debug/Test Methodology+11
2.3.2.1 IEEE 1149.1 Standard(JTAG)+11
2.3.2.2 In-Circuit Emulator+13
2.4 Real Case of SW/HW Co-Debugger+15
2.4.1 Multi-Core SW/HW Debug Platform+15
2.4.2 ARM Developement Tool Chain+16
Chapter 3 The Proposed Method+19
3.1 Motivation of Proposed Method+19
3.2 System Overview of Proposed Method+20
3.2.1 Limitation of Proposed Method+22
3.3 Hardware Part of the proposed Platform+22
3.3.1 Socket-base Interface Protocol+22
3.3.2 Wrapper-Base In-Circuit Emulator+23
3.3.3 Daisy Chained With Embedded In-Circuit Emulator+26
3.4 Software Part of the proposed Platform+27
3.4.1 Control Flow of the proposed Platform+28
3.4.2 GDB-JTAG Adapter+29
3.4.3 Remote Debugging by GNU Debugger+30
3.4.4 Open On-Chip Commands for HW Control+32
Chapter 4 Experimental Results 35
4.1 Verification of WBICE+35
4.1.1 Experiment Environment Setup+35
4.1.2 TAP Finite State Machine Functional Verification+36
4.1.3 Instruction Decode Functional Verification+38
4.1.4 Breakpoint and Resume Functional Verification+41
4.2 Area Report for WBICE+43
Chapter 5 Conclusion+44
Chapter 6 Future Works+45
Bibliography+46
Appendix A Wrapper-Base ICE RTL Test Tasks+48

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