現今單一面積晶片的功能日益繁多，導致系統單晶片(SoC)整合時的驗證與除錯工作也更加複雜且困難，矽智產(IP)開發者在設計時皆會個別驗證硬體，但將多個IP整合在一SoC環境時，IP之間的傳輸問題便會浮現；部分文獻會設計一個特別訂製的匯流排傳輸監控器，以檢測是否有非預期的行為發生，加速並協助SoC整合與驗證工作，但在維護或修改此類監控硬體是相當費力且耗時的，因此我們開發出一套可重複設定之匯流排監控器套件(Reconfigurable Bus Monitor Tool Suite)；此套件之監控硬體有別於過去特別訂製的監控器器，此套件之硬體提供使用者設定任何想要監控的斷言(assertion)，監控的對象包含協定錯誤檢測、效能監控與特殊狀態監控三類，提供一套監控傳輸上協定與效能的監控硬體給SoC整合者，提高他們對硬體的掌握程度。
但要如此有彈性的監控硬體，其所占面積必定比特殊制定的監控器還要大上許多，針對此問題，我們分析組成斷言功能所會用到的基本元件，將之做分類與統整，並將硬體實作參數化，開發一套可自動產生此監控硬體的產生器，開發者可依自己的需求或環境限制，選擇自己適用的監控器功能；可設定較多與較複雜的監控器，斷言設定的彈性較高，產生後的硬體面積也較大；反之監控器的功能較陽春者，雖然可設定的斷言彈性低，但硬體面積也相對較小。此工具套件不僅適用於RTL模擬，在FPGA與post-silicon階段的驗證更能發揮其最大的功能，適用於晶片設計各階段，協助晶片系統整合驗證與除錯硬體，並加速晶片出廠時間。

Today, due to the process of semiconductor improve rapidly, the number of transistors and functions in the same area of a chip becomes more than before. The integration and verification for System-on-Chip (SoC) will also be more complex. Although IP has verified carefully by the IP designer, but the bus transaction problem may occur during integration. Previous researches have proposed a hard-wired bus monitor to detect the unexpected transaction condition. But maintain and revise such hard-wired monitor take big effort. So we develop a tool which make designer’s integration and verification easier – Reconfigurable Bus Monitor Tool Suite (RBMTS). It contains 2 software GUI and 1 hardware monitor. Designers can configure the bus condition they wonder to monitor as assertions into the Reconfigurable Bus Monitor (RBM) hardware. It can monitor not only bus protocol, but also bus transaction performance or some specific event. Such a flexible hardware monitor may encounter the high-area cost problem. We analyze the implementation of assertions first, and then parameterized the implementation to develop an RBM hardware generator for designer to choose generate it. User can decide the function of RBM according to their SoC environment. The configuration and analysis GUI helps designers configure the assertion control into hardware and analyze the result. The monitor is for both pre-silicon and post-silicon debug purpose. This really reduces critical time-to-market time and turnaround time for today’s IC design.

Chapter 1. Introduction+1
1.1 Background+1
1.2 Motivation+2
Chapter 2. Related Works+6
2.1 Rule-Based Bus Protocol Checker+6
2.2 Synthesizable High Level Assertion Checker+8
2.3 Trigger Unit for Post-Silicon Validation+9
2.4 PAU (Performance Analysis Unit)+10
2.5 Current Commercial Tool+12
Chapter3. Simple Hardware Monitor Organization of RBMTS+15
3.1 Overview of RBMTS+15
3.2 RBM Hardware Component: Signal Selecting Module (SSM)+18
3.3 RBM Hardware Component: Event Generation Module (EGM)+20
3.4 RBM Hardware Component: Event Combination Module (ECM)+23
3.5 RBM Hardware Component: Event Sequencing Module (ESM)+28
Chapter 4. Width-Classified Hardware Monitor Organization of RBMTS+32
4.1 Area Problem of Simple RBM Hardware+32
4.2 Width-Classified RBM Hardware component: Signal Selecting Module (SSM)+32
4.3 Width-Classified RBM Hardware component: Event Generator Module (EGM)+35
4.4 Width-Classified RBM Hardware component: ECM and ESM+36
4.5 Summary of RBM Hardware and Configuration Limitation+37
Chapter 5. Status Controller and RBM History Buffer+39
5.1 RBM Status Controller+39
5.2 RBM History Buffer+42
5.2.1 Match History Buffer+42
5.2.2 Performance History Buffer+43
5.3 configuration limitation of RBM hardware +44
Chapter 6. RBM Generator Tool and RBM Configuration/Analysis Tool in RBMTS+45
6.1 RBM Generator Tool+45
6.2 RBM Configuration/Analysis Tool+48
Chapter 7. Experiment Result in AXI-based 3D Graphic SoC+50
Chapter 8. Conclusion and Future Work+51
Reference+52
Appendix A: Area and Latency Analysis of RBM Hardware+54
A.1 Area of Signal Selection Module (SSM)+54
A.2 Area of Event Generator Module (EGM)+55
A.3 Area of Event Combination Module (ECM)+56
Appendix B: Case Study of RBM Assertion+57
B.1 AXI Protocol Checker Case Study of RBM Implementation and Configuration+57
B.2 Performance Metrics Case Study of RBM Hardware Implementation and Configuration+64

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