隨著微處理器的發展採用更多技術來增加效能使微處理器更加複雜，並且導致驗證微處理器的行為更加困難，如何利用正確的微處理器來協助驗證在相同的指令集下之開發中的微處理器以減少驗證和除錯時間。
結合多個冗餘的模組去偵測執行中的暫態錯誤或永久錯誤的容錯機制已被廣泛運用在車用、航空等電子。把此容錯概念運用在一顆正確的處理器和一顆開發中的處理器所建構成雙核心的架構下，將正確的微處理器當作範本對開發中的微處理器進行驗證，一旦偵測到雙方的資料不同就立即停止雙核的運作，讓處理器停住在發生錯誤的時間點附近以利除錯。首先實驗同樣架構但不同設計的兩個微處理器是否能正確擷取資料，另一個實驗用不同快取大小和替換機制的兩個快取記憶體作驗證此方法的可行性，並且將錯誤發生在處理器核心、指令快取記憶體和資料快取記憶體上仍可偵測到錯誤，最後此方法的效能比單一核心降低上約30%。

For improving the performance of microprocessor becomes more and more complex with the microprocessor techniques improvement. This improvement leads to verify microprocessor behaviors that becoming more and more difficult. How use the complete microprocessor to verify the developing microprocessor for decreasing time of debugging?
The fault tolerance which is duplicating same components to detect transient faults and permanent faults at running time is widely used in the automobile or aviation electrons. This fault tolerance concept is used to verify the developing microprocessor with the complete microprocessor which is a golden in the dual core architecture. Both microprocessors are suspended when both data are inconsistent and the fault is occurred near the executing instruction to help debugging. We design two experiments to verify our methodology that can be implemented, one uses the same instruction set architecture with different implementation on two independent processors, the other is that using the same processor but with different cache size and replacement policy. Second, the microprocessor is injected faults in the core, instruction cache and data cache and our methodology can detect the faults normally. Final, the performance degradation of our methodology is 30% with a single core.

論文審定書+i
論文聲明書+ii
致謝+iii
中文摘要+v
Abstract+vi
Chapter 1 Introduce+1
1.1 Motivation+1
1.2 Comparing with two independent processor environments+2
1.3 S32TME+2
1.4 S32TME3+3
Chapter 2 Related Works+4
2.1 Fault tolerance+4
2.2 Processor Verification+7
2.2.1 Processor Core Verification+7
2.2.2 Cache Verification+8
2.3 Relationship between our work and related work+10
Chapter 3 Dual Core Verification platform and its challenges+12
3.1 Overview+12
3.2 Challenges+14
3.2.1 Selection of Visible Signals+15
3.2.2 Synchronization between Dual Cores+17
3.2.3 The Organization of Event Queue+19
3.2.4 Data Bandwidth of Core+20
Chapter 4 Organization of the Dual Core Verification Platform+22
4.1 Load/Store Queue+22
4.1.1 Request Receiver+24
4.1.2 Queue buffer+25
4.2 Verification controller+26
Chapter 5 Experimental results+30
5.1 Same architecture with different implementation comparison+30
5.2 Different cache comparison+31
5.3 Fault detection with two identical S32TME+32
5.4 Fault detection with an S32TME and S32TME3+35
5.5 Performance degradation+42
Conclusions and Future Work+46
Appendix A : Verification patterns+47
A.1 Forward unit+47
A.2 Data abort+49
Reference+52

[1] ARM7TDMI Data Sheet, ARM Ltd., 1995.
[2] Y.-W. Sung, "Microprocessor Evaluation and Improvements of ARM Microprocessor's Architecture Features," in Master's thesis, National Sun Yat-sen University, 2003.
[3] ARM1022E Technical Reference Manual, r0p2 ed., ARM Ltd., 2001.
[4] C.-C. Hu, "Design and Implementation of an ARM10-like Microprocessor," in Master's thesis, National Sun Yat-sen University, April 2008.
[5] J.-K. Zhong, "The Design Verification Methodology for an Advanced Microprocessor," National Sun Yat-sen University, August 2008.
[6] C.-S. Lin, "Design and verification of an ARM10-like Processor and its System Integration," in Master's thesis, National Sun Yat-sen University, JJanuary 2012.
[7] S. K. Reinhardt and S. S. Mukherjee, "Transient Fault Detection via Simultaneous Multithreading," Proceedings of the 27th annual international symposium on Computer architecture(ISCA'00), pp. 25-36, 2000.
[8] S. S. Mukherjee, M. Kontz and S. K. Reinhardt, "Detailed Design and Evaluation of Redundant Multithreading Alternatives," Proceedings of the 29th Annual International Symposium on Computer Architecture (ISCA’02), 2002.
[9] P. Subramany an, V. Singh, K. K. Saluja and E. Larsson, "Multiplexed Redundant Execution: A Technique for Efficient Fault Tolerance in Chip Multiprocessors," Design, Automation & Test in Europe Conference & Exhibition (DATE), 2010.
[10] A. Golander, S. Weiss and R. Ronen, "Synchronizing Redundant Cores in a Dynamic DMR Multicore Architecture," IEEE Transactions on Circuits and Systems II: Express Briefs, pp. 474-478, June 2009.
[11] A. Paschalis and D. Gizopoulos, "Effective Software-Based Self-Test Strategies for On-Line Periodic Testing of Embedded Processors," Proceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE’04), 2004.
[12] F.-C. Yang, W.-K. Huang, J.-K. Zhong and I.-J. Huang, "Automatic Verification of External Interrupt Behaviors for Microprocessor Design," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp. 1670-1683, Sept. 2008.
[13] G. Theodorou, N. Kranitis, A. Paschalis and D. Gizopoulos, "A Software-Based Self-Test Methodology for In-System Testing of Processor Cache Tag Arrays," Proceedings of On-Line Testing Symposium (IOLTS), IEEE 16th International, pp. 159-164, 5-7 July 2010.
[14] G. Theodorou, N. Kranitis, A. Paschalis and D. Gizopoulos, "A Software-Based Self-Test Methodology for On-Line Testing of Processor Caches," Test Conference (ITC), 2011 IEEE International, pp. 1-10, 20-22 September 2011.
[15] Y. Lin, Y.-Y. Tsai, K.-J. Lee, C.-W. Yen and C.-H. Chen, "A Software-Based Test Methodology for Direct-Mapped Data Cache," Proceedings of Asian Test Symposium , pp. 363-368, 24-27 Nvember 2008.
[16] W. J. Perez H., D. Ravotto, E. Sanchez, M. S. Reorda and A. Tonda, "On the Generation of Functional Test Programs for the Cache Replacement Logic," Asian Test Symposium, 2009. ATS '09, pp. 418-423, 23-26 Nov. 2009.
[17] C.-C. Chen, "The Linux Porting and Integration Verification of An Academic 32-bit Processor," in Master's thesis, National Sun Yat-sen University, September 2012.
[18] ISE Design Suite: System Edition, Xilinx Ldt., 2010.
[19] ARM Developer Suite Developer Guide, ARM Ltd., 2001.