在通訊系統中，為了避免受到雜訊或是通道本身特性所干擾，並且符合整體的系統需求和提高傳輸資料的正確率，錯誤更正碼已成為通訊系統中不可或缺的模組，扮演了一個舉足輕重的角色。在眾多錯誤更正碼當中，目前全世界擁有最好錯誤更正能力的便是極化碼，其解碼效能達到通訊理論上的香濃極限。因此極化碼提出以來，迅速成為通訊領域的一個研究熱點，甚至納入下一世代5G通訊系統的標準之中，成為通訊產業上不可或缺的關鍵技術之一。
本論文提出可變量長度的先進先出回授機制，將整體編碼器架構摺疊成數級的模組化單元。在運算單元中，以簡單的互斥邏輯閘為主要計算元件，並搭配可變量長度的儲存單元，提出Radix-2 極化編碼器。並且再進一步改進其性能，發展出Radix-2 超高速平行化極化編碼器及可重置性多模式極化編碼器之硬體架構。利用TSMC 90nm CMOS製程來實現硬體，所提出的編碼器架構擁有高運算速度、高吞吐量及低面積成本等特性之晶片設計架構。這樣高效率低面積且模組化的設計期許能符合下世代5G行動標準之高速率、高吞吐量及高可靠度的標準，並且支撐未來豐富的無線物聯網的應用。

In the communication system, Error Correcting codes (ECC) would become a necessary and important module because it can prevent from the noise disturbance and eliminate the channel response effects. Therefore, it plays a critical role due to meeting the overall system requirement and enhancing data transmission correctness. Among so many kinds of ECC, the one behaving the best error correcting ability in the world is Polar Codes. In the communication theory, its decoding performance is very close to the lower bound, Shannon Limit. As a result, it has been a research spotlight in a rapid progress way. Even more, it will be considered as an indispensable key part in communication and adopted in next-generation 5G applications.
This thesis proposes the Variable-Length FIFO Feedback Architecture. By applying regular and scalable characteristics, the overall encoder architecture can be folded into several stages of modular units. Our proposed radix-2 Polar encoder hardware architecture is composed of some simple XOR gates and variable-length storage units. And then in order to further improve its performance, we propose 32-parallel radix-2 Polar encoder and reconfigurable multi-mode Polar encoder hardware architecture. Our work achieves high-speed and low-area-cost efficient Polar encoder chip, implemented with TSMC 90nm CMOS technology. This low-area-cost, low power dissipation, and high-performance hardware architecture can achieve the requirement of the future wireless communication system and support the future of the rich application of internet of things.

論文審定書 i
誌謝 ii
摘要 iii
Abstract iv
目錄 v
圖次 vii
表次 x
第一章 緒論 1
1.1 研究背景與動機 1
1.2 論文架構 5
第二章 極化碼 6
2.1 二進制離散無記憶通道特性 6
2.2 通道極化理論 6
2.2.1 通道組合 7
2.2.2 通道分解 9
2.2.3 通道極化 11
2.3 極化碼的建置 12
2.3.1 生成矩陣 12
2.3.2 極化碼的構造 14
第三章 可變量長度的先進先出回授架構極化編碼器之VLSI實現 15
3.1 Radix-k 可變量長度的先進先出回授極化編碼架構 15
3.1.1 Radix-2的設計 15
3.1.2 Radix-4的設計 19
3.1.3 Radix-8的設計 23
3.1.4 推廣至Radix-k 的設計 30
3.2 多輸入多輸出之極化編碼器 32
3.2.1 Radix-2之32倍超高速平行化設計 32
3.3 可重置性多模式極化編碼器 34
3.3.1 Radix-2 /Radix-4 可重置性的設計 34
3.3.2 Radix-2 /Radix-4 /Radix-8 可重置性的設計 37
第四章 晶片實現 39
4.1 合成結果 39
4.1.1 Radix-2 極化編碼器 39
4.1.2 Radix-2之32倍超高速極化編碼器 41
4.1.3 Radix-2 /Radix-4 /Radix-8 可重置性極化編碼器 42
4.1.4 各種極化編碼器之比較 43
4.2 可測試性設計 45
4.2.1 Radix-2極化編碼器 46
4.2.2 Radix-2之32倍超高速極化編碼器 47
4.2.3 Radix-2 /Radix-4 /Radix-8 可重置性極化編碼器 49
4.3 佈局結果 50
4.3.1 Radix-2極化編碼器 50
4.3.2 Radix-2之32倍超高速極化編碼器 51
4.3.3 Radix-2 /Radix-4 /Radix-8 可重置性極化編碼器 52
4.4 效能比較 52
第五章 結論 55
參考文獻 56

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