現今科技產品於立體視覺、影像、通訊等相關的應用中，都會使用到一些特殊函數的運算。以硬體實作各類特殊函數的近似法中，最常被使用的方法為多項式逼近法，此方法是將原本連續函數的曲線，分割成多個子區間、並於各個子區間內，將多項式係數儲存於ROM表中，以查表方式，進行多項式的逼近。在提升精確度的同時，多項式可由原本的二階增長到三階，以避免表格變大，但其架構內部使用的三方器會造成總體面積大幅增加。因此，本論文採取數學領域中，經常用於高階多項式的霍那法，其作法為透過疊代的方式，減少多項式中的計算量，其硬體方面則是由乘法器及加法取代了平方器、三方器等，優點為減少硬體面積，缺點為疊代運算，使得硬體運算延遲變長，而為了減少運算時間，我們將提出改良的霍納法，經比較後的結果為相對於原本三階多項式的架構中，以16bits、24bits精確度的倒數函數為例，速度變快約14%、面積大幅減少約50%；於32bits精確度時，速度雖然變慢1%、但面積則減少了約67%。另外，產品的功率消耗限制也更加嚴苛，可由不同精確度的切換中，減少部分硬體運算，並於高精確度的表格中，達成較低精確度的表格需求，減少功率消耗，而本論文將使用前述提出的改良版霍那法架構應用於四重精確度的設計中。

Computation of special functions is widely used in many applications such as stereo vision, image processing, and communication. Piecewise polynomial approximation (PPA) is usually adopted in hardware implementation of special function computation where the coefficients of polynomials that approximate the function in the partitioned input segments are stored in lookup tables (LUT). Optimization of LUT or arithmetic components are the major design considerations in hardware function evaluation. In this thesis, we will focus on the low-cost and low-power design of hardware function evaluation that supports dynamic multiple precisions. In high-precision requirements such as 32-bit accuracy, the degree of per-segment approximation polynomial is usually increased to three in order to reduce the LUT size. However, the involving arithmetic components become more complicated. This thesis proposes several different architectures based on Horner’s rules with iterative computation of lower-degree polynomials, and compare the performance in area, delay and power consumption. Finally, we select the architecture with improved Horner’s rule. In the example of reciprocal function computation with degree-three PPA, the proposed design has area saving rate of up to 60% while almost maintaining the same delay compared with the direct implementation of degree-three polynomials. In dynamic multi-precision computation, t unused LUT and arithmetic components are turned off in order to reduce power consumption in low-precision modes.

目錄
論文審定書 i
摘要 iv
Abstract v
目錄 vi
圖目錄(List of Figures) viii
表目錄(List of Tables) xi
第一章、導論 1
1.1 研究動機 1
1.2 論文架構 1
第二章、研究背景與相關研究 3
2.1 ANSI/IEEE Std. 754-1985浮點數標準 3
2.1.1 各類函數浮點格式表示及應用 5
2.2查表法(Look-up Table Methods) 7
2.3間接查表法分類 (In-direct Look-up Table Methods Classification) 9
2.3.1 Computed-Bound Methods 9
2.3.2 Table-Bound Methods 10
2.3.3 In-between Methods 13
2.4函數近似分段查表法(Function Approximation with Piecewise Table method) 14
2.4.1函數區間定義(Definition of function approximation) 16
2.4.2計算分割間距(Calculate the number of subinterval) 17
2.4.3係數產生方式(Coefficients generation) 18
2.5截斷式乘法器(Truncated Multiplier) 21
2.5.1截斷式乘法器修正誤差方法 23
2.5.1.1變數修正法(Variable Correction) 24
2.5.1.2常數修正法(Constant Correction) 25
2.5.2壓縮樹(Tree Compression) 26
2.5.3平方器(Squarer) 29
2.5.4三方器(Cuber) 31
2.6誤差分析方法(Error Analysis Methods) 33
2.6.1預先設定誤差(Error Budget) 33
第三章、三階插值多項式使用改良霍納法之架構與設計 36
3.1三階插值硬體架構(Original Cubic Interpolator Architecture) 37
3.2傳統霍那法之硬體架構(Original Horner’s Rule Architecture) 43
3.3 Horner’s Rule Transformation Architecture - I 48
3.4 Horner’s Rule Transformation Architecture - II 52
3.5 四種架構之面積、速度數據 56
第四章、定點數多重精確度之架構與設計 67
4.1實現多重精確度硬體之算術與表格共用設計 71
4.1.1算術電路共用 75
4.1.2表格共用 80
4.2 Multiple Precision Architecture with Original Cubic Interpolation 87
4.3 Multiple Precision Architecture with Original Horner’s Rule 90
4.4 Multiple Precision Architecture with Horner’s Rule Transformation I 92
4.5 Multiple Precision Architecture with Horner’s Rule Transformation II 94
第五章、實驗結果比較與分析 96
5.1四重精確度架構(8、16、24、32bits)合成之數據比較 96
5.2四重精確度架構(8、16、24、32bits)合成Power數據比較 106
第六章、結論與未來展望 115
6.1 結論 115
6.2 未來展望 116
參考文獻 117

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