在現今的許多嵌入式系統應用之中，設計者都偏好使用較省電的浮點乘法單元。在本論文中，我們提出了一個可變延遲(variable latency)之浮點乘法單元架構。它適合使用於低功率消耗、高效能以及高精確度的應用設計之中。此架構將有效數乘法器(significand multiplier)分成上、下兩半部，並且從上半部的有效數乘法器中，預測所需要的有效數乘積(significand product) 和黏著位元(sticky bit)。當可預測正確時，下半部的計算就可以運用時脈閘控使其不作運算，有助於節省功率消耗。此預測機制同時也可以將捨入模式(rounding mode)更加的簡化，幫助浮點乘法運算可以提早完成。
最後，我們詳細描述所提出之浮點乘法器的細部架構，並且將提出的雙精度浮點乘法單元與傳統式以及快速式的浮點乘法單元的功率消耗做比較。實驗結果顯示我們所提出的雙精度浮點乘法單元只比快速式的浮點乘法單元多出些許的面積及延遲，卻可以分別減少最多26.41%以及24.97%的功率消耗與能量消耗。實驗結果亦顯示我們所提出的浮點乘法單元的效能非常接近快速式浮點乘法單元的效能。因此，我們的浮點乘法單元亦非常適合使用於高速的浮點乘法應用上。

Floating-point multipliers are typically power hungry which is undesirable in many embedded applications. This paper proposes a variable-latency floating-point multiplier architecture, which is suitable for low-power, high-performance, and high-accuracy applications. The architecture splits the significand multiplier into upper and lower parts, and predicts the required significand product and sticky bit from upper part. In the case of correct prediction, the computation of lower part is disabled and the rounding operation is significantly simplified so that floating-point multiplication can be completed early.
Finally, detailed design and simulation of the floating-point multiplier is presented, together with its evaluation by comparing power consumption with the fast and conventional floating-point multipliers. Experimental results demonstrate that the proposed double-precision multiplier consumes up to 26.41% and 24.97% less power and energy than the fast floating-point multiplier respectively at the expense of only small area and delay overhead. In addition, the results also show that the performance of proposed floating-point multiplier is very approximate to that of fast floating-point multipliers.

Contents
Chapter 1 Introdution
1.1 Motivation
1.2 Contribution
1.3 Organization
Chapter 2 Background and Related Work
2.1 IEEE Floating-Point Multiplication
2.2 Compression Tree
2.3 Rounding Modes
2.4 Related Work
2.5 Low power technique
Chapter 3 Low Power Floating-Point Multiplication Algorithm
3.1 Low Power Floating-Point Multiplication
3.2 Prediction of c0 and r
3.3 Prediction of s
3.4 Proposed Algorithm
Chapter 4 Rounding and Normalization of Proposed Algorithm
4.1 Rounding and Normalization
4.2 RNE Mode
4.3 RI and RZ Mode
4.4 Rounding for Exact Prediction Chapter 5 Implementation and Results
5.1 Architecture of Proposed Multiplier
5.2 Add-one Circuit and Carry-Select Adder
5.3 LPm
5.4 ORL
5.5 Parallel-Prefix Adder
5.6 Results
Chapter 6 Conclusion and Future Work
6.1 Conclusion
6.2 Future Work
References

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