由於半導體製程持續往高密度積體電路（Integrated Circuit, IC）的發展，進而許多研究開始投入2.5維與3維IC的封裝技術。在2.5維IC的結構中，銅柱焊接製程已慢慢成為主流的接合製程。近來，發現在銅柱焊接製程時，會有虛焊缺陷的情形，目前業界認為造成此缺陷的主要原因可能為結構受熱後的翹曲所致。
本研究主要透過有限元素法建立2維之2.5維IC模型，模擬迴焊製程中所產生的翹曲對於銅柱接合的影響，且藉由ANSYS脫黏的設定，找出銅柱脫黏與產生裂縫的接合力範圍。最後藉由改變矽晶片層的厚度、銅柱的材料結構與迴焊溫度，探討其對於IC整體的翹曲與接合力範圍之影響。
由模擬結果可知，在不考慮對位不準的條件下，依據本研究所採用之數值模擬模型顯示，若接合力大於285MPa則不會有裂縫產生；若接合力小於50MPa則會發生脫黏。矽晶片層厚度方面，與矽晶片層厚度為50um時相比，當矽晶片層厚度為100um與150um時，其產生裂縫的臨界接合力約上升了14與30%，翹曲量則約上升了13.53與25.05%。銅柱材料結構方面，鎳層的加入，直接降低了整體的翹曲量，以及臨界接合力的提高，以Type 3來說，與原模型相較，其臨界接合力提高了8.77%，翹曲則是降低了0.77%；而金層的加入，有助於降低鎳層所帶給焊料的應力集中，進而降低接合之臨界接合力，以Type 5來說，比起沒有金層的Type 3，其臨界接合力下降了4.84%。溫度效應方面，與迴焊溫度為100oC相比，當迴焊溫度為150oC、200oC與240oC時，其產生裂縫的臨界接合力呈非線性地上升了31.71、36.59與39.02%，翹曲量方面大致隨溫度上升呈線性遞增46.47、74.83以及77.89%。

As the semiconductor manufacturing industry continue to develop high-density integrated circuits （IC）, many studies of 2.5D and 3D IC packaging technology are being carried out. The copper pillar bump bonding process has become the mean means of fabricating 2.5D IC structures. Recently, cold joint defects have been detected in copper pillar welding. Currently the industry believes that structural warping by heating is likely to be the main cause of the formation of defects.
This work establishes a two-dimensional model of the 2.5D IC by using the finite element method to simulate the impact of bonding with warping on welding process, and determines the range of bonding forces when copper pillars debond and generate cracks, using the debonding setting in ANSYS. Finally, the impact of an IC on warping and the range of bonding forces is studied by changing the thickness of the die layer, the material structure of the copper pillars, and the reflow temperature.
The results of the numerical simulation model that is used in this research, which does not consider the alignment show that when the bonding force exceeded 285MPa, no crack appeared. When the bonding was less than 50MPa, debonding occurred. Compared with 50um thickness of the die, when the thickness was changed to 100 and 150um, the critical bonding forces of crack were increased by 14 and 30%, respectively, and the warpages were increased 13.53 and 25.05%, respectively. Adding a nickel layer to the copper pillars directly reduced the overall warpage and increased critical bonding force. For example, the layer improved the critical bonding force of type 3 by 8.77%, reduced the warpage by 0.76%. Adding the gold layer reduced the stress concentration in the solder that was caused by the nickel layer, reducing the critical bonding force; the type 5 had a 4.84% lower bonding force that the type 3, which had no gold layer. Compared with 100oC of reflow temperature, when the temperature was changed to 150, 200, and 240oC, the critical bonding forces were increased by 31.71, 36.59 ,and 39.02%, respectively, and the warpages were increased approximately linearly with temperature by 46.47, 74.83 and 77.89%, respectively.

目錄
誌 謝 ii
摘 要 iii
Abstract iv
目錄 vi
表目錄 ix
圖目錄 xii
第一章 緒論 1
1.1 前言 1
1.2 電子封裝之發展[8] 2
1.2.1 2.5D IC封裝技術簡述 3
1.2.2 IC封裝翹曲成因及翹曲定義 3
1.2.3銅柱焊接製程簡介[7, 13-15] 4
1.3 文獻回顧 5
1.3.1 銅柱焊接製程之優點 5
1.3.2 銅柱焊接製程之缺點 6
1.3.3 銅柱焊接製程之改善 8
1.4 錫材料簡介[46] 10
1.5 研究動機與目標 10
1.6 全文架構 11
第二章 基礎理論介紹 21
2.1 有限元素法簡介[55] 21
2.2套裝軟體ANSYS 15.0/Workbench簡介[56, 57] 22
2.2.1變形理論 25
2.2.2脫黏理論（Debonding） 26
2.3連續多重耦合分析介紹 27
第三章 研究方法 33
3.1假設條件 34
3.2 模擬模型之建構與設定 35
3.2.1 元素模型與材料模型選用 35
3.2.2 模擬模型之結構與尺寸 36
3.2.3 材料參數設定 36
3.2.4 網格劃分 37
3.2.5 邊界條件、負載方式與接觸設定 37
3.2.6網格收斂性分析 38
第四章 結果與討論 51
4.1 模擬結果分析 51
4.1.1 接合力對翹曲量之影響 52
4.1.2 接合力對接合面之影響 53
4.1.3 接合力對焊料之影響 53
4.2 矽晶片層厚度之影響 54
4.3 銅柱材料結構之影響 55
4.4 迴焊溫度之影響 57
第五章 結論與未來展望 96
5.1 結論 96
5.2 未來展望 97
參考文獻 98

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