此全數位鎖定迴路(All-Digital Delay-Locked Loop，ADDLL)使用TSMC 90nm製程，採用數位相位偵測器(Digital Phase Detector，DFD)和連續近似暫存器(Successive Approximation Register，SAR)來控制數位延遲線(Digital Delay Line，DDL)以及一些控制單元(Control Unit)所組成。在全數位鎖定迴路裡，設計數位延遲線會是一個關鍵，它將影響整個全數位鎖定迴路的效能。延遲線的部分採用互補延遲線的方式來提高可鎖定的範圍，利用粗調及微調的方式來提高延遲的精準度，並且可以節省數位延遲線使用的電源，達到降低功率消耗和節省晶片面積。此全數位鎖定迴路採用10位元的逐次逼近暫存器來實現快速鎖定，並使用溫度計碼降低功率消耗及提升線性度。另外，在使用傳統式的連續近似暫存器，將因為在製程、電壓和溫度變異的環境中無法對電路做持續追蹤而造成電路的不正確，而為了避免全數位鎖定迴路死鎖的問題，因此會使用改良式連續近似暫存器來克服所面臨的問題，讓數位鎖定迴路在鎖定之後能夠持續對電路做追蹤。另外，可鎖定的範圍約從140 MHz到1 GHz，供應電壓為1 V，具有大約3.54 ps的延遲解析度，在1.4 GHz功率消耗為1.535 mW，時脈抖動(Jitter)在1.4 GHz為4.89 ps，鎖定時間在1 GHz為20個時脈週期。

This All-Digital delay-locked loop uses TSMC90nm process. It uses digital phase detector and successive approximation register to control the digital delay line as well as some control units. The digital delay line is the key component of performance. The part of delay line uses a complementary way to improve the locking range and using coarse and fine tune to improve the resolution of delay. The digital delay line has low power consumption, small area, and high resolution. This ADDLL implements a 10-bit successive approximation register to achieve the fast locking and thermometer code to reduce power and improve linearity. In addition, the ADDLL may unlock caused by the process, voltage, and temperature (PVT) variations when it uses a conventional successive approximation register. An improved successive approximation register is proposed to overcome the problem caused by the dead lock. In addition, the simulated locking range is starting from 140 MHz to 1 GHz. The supply voltage is 1 V. The delay resolution is about 3.54 ps. The power is 1.535 mW at 1.4 GHz. The jitter is 4.89 ps at 1 GHz. The locking time of the proposed ADDLL is 20 clock cycles at 1 GHz.

論文審定書 i
中文摘要 ii
ABSTRACT iii
目錄 iv
圖目錄 vii
表目錄 x
第1章 緒論 1
1.1 研究動機 1
1.2 論文組織架構 2
第2章 延遲鎖定迴路簡介 3
2.1 鎖定迴路的應用 3
2.1-1 抑制時脈偏移 3
2.1-2 降低時脈抖動 4
2.2 鎖定迴路基本架構 5
2.3 延遲鎖定迴路的效能指標 6
2.3-1 靜態相位誤差(Static Phase Error) 6
2.3-2 操作範圍(Operating range) 7
2.3-3 鎖定時間(Locking Time) 7
2.3-4 時脈抖動(Jitter) 7
2.3-5 延遲解析度(Resolution) 8
2.4 延遲鎖定迴路 8
2.5 數位延遲鎖定迴路 11
第3章 數位延遲鎖定迴路設計 18
3.1 系統架構 18
3.2 相位偵測器 20
3.3 控制單元 23
3.3-1 具有持續追蹤之改良式連續近似暫存器 23
3.3-2 範圍選擇單元 27
3.3-3 時脈選擇單元 27
3.3-4 二進位至溫度計碼解碼器 28
3.3-5 除頻器 32
3.4 數位延遲線 33
3.4-1 粗調延遲線 33
3.4-2 細延遲線 34
第4章 數位鎖定迴路模擬 35
4.1 數位相位偵測器模擬 35
4.2 改良式連續近似暫存器模擬 36
4.3 數位延遲線模擬 37
4.3-1 延遲線線性度 37
4.3-2 延遲解析度 38
4.4 鎖定迴路模擬 40
4.5 時脈抖動模擬 41
4.6 靜態相位誤差模擬 43
4.7 電路規格與比較表 44
第5章 數位鎖定迴路晶片實現 46
5.1 晶片佈局(Layout) 46
第6章 結論與未來研究 48
6.1 結論 48
6.2 未來研究 48
參考文獻 49

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