失真壓縮方法常用來減少除錯資料，擁有高壓縮率與易於實現的優點。現今的系統晶片除錯方法常會壓縮無錯電路(目標簽章) 與待測電路 (模擬簽章) 的追蹤資料，並比較兩者簽章辨識出可疑的錯誤事件 (週期編號) ，但通常會導致較差的辨識精準度，意味著可疑的錯誤事件中只有小部分是真正的錯誤事件。
因此，我們提出一多維度壓縮的偵錯方法，透過彙整多維度簽章，將可改善辨識精準度。且提出一整合開發平台，讓設計者可以量身定做出合適的配置(軟硬體模組組合及硬體結構)，(1)模組化之多維度壓縮的偵錯方法(軟體模組與硬體模組)，可讓使用者依照時間成本，硬體成本，即時追蹤等需求，任意組合出最適合的使用場景。並且展示一參數化及管線化之多維度壓縮的除錯方法硬體實作；(2)多維度壓縮的偵錯方法架構之探勘工具，藉由我們所提出之評估指標來探勘各種架構(壓縮方法，維度數量與視窗大小，視窗大小表示為使用多少個週期來做壓縮)，且依照設計者所預期的指標參數來幫助設計者找出最適當的架構，並提供一自動產生器並且產生出對應之多維度壓縮的除錯方法硬體以及目標簽章。

Lossy compression (compaction) methods are often used to reduce debugging data, which has high compression ratio and easier to implement. The system-on-chip (SoC) debugging methodology uses the signal trace compaction of bug-free design-under-debug (DUD’s) golden model (golden signatures) and DUD’s hardware (simulated signatures) and then compares both signatures to identify the suspected buggy events (cycle number) for DUD hardware. However, this will lead to low identification precision, which means that only a small part of the suspected buggy events are actual buggy events.
Therefore, we proposed a multi-dimensional compaction-based debugging methodology (MDCBDM) to improve the identification precision by multi-dimensional signatures intersecting. Moreover, we provide an integrated development environment (IDE), which allows a designer to make the most suitable configuration (combination of HW/SW modules and HW structure). The IDE includes: 1) a modularized MDCBDM that contains HW/SW modules, which can be arbitrarily combined into various scenarios to meet the different designer requirements of time cost, hardware cost and real-time tracing. Moreover, we demonstrate a parameterized and pipelined MDCBDM HW implementation; 2) an MDCBDM HW structures exploration tool that can explore various structures (compaction methods, dimension, and window size, the window size is express group cycles to compute the multi-dimensional compaction) by our proposed metrics. Moreover, the exploration tool can get the most suitable structure for the designer expected metrics, and then generated both MDCBDM HW and golden signatures of this structure by our provided automatically generator.

論文審定書 i
中文摘要 iii
Abstract iv
Chapter 1. Introduction 1
1.1 Background 1
1.2 Motivation 3
1.3 Organization of the Thesis 6
Chapter 2. Related Works 7
2.1 DFD methodologies 7
2.2 Signal Trace Compression Methods 8
2.3 Deterministic Debug techniques with signature 9
Chapter 3. Modularized Multi-Dimensional Compaction-Based Debugging Methodology 12
3.1 Modularized MDCBDM Framework 13
3.2 A Modularized MDCBDM with Hardware and Software Modules 14
3.2.1 Software Modules 14
3.2.2 Hardware Modules 14
3.3 Case Study 15
3.3.1 Hardware Cost-Efficient Case 15
3.3.2 Fast Identify SBEs Case 16
3.3.3 Fast Identify and Real-Time Tracing SBEs Case 17
Chapter 4. Parameterized Multi-Dimensional Compaction-Based Debugging Methodology HW Architecture 18
4.1 Data Organization of MDCBDM Hardware Architecture 19
4.2 Debug Flow of MDCBDM Hardware Architecture 20
4.3 Pipelined Structure 21
4.3.1 Space Compaction 21
4.3.2 Time Compaction Stage 22
4.3.3 Signature Comparison Stage 23
4.3.4 Suspected Event Identification Stage 23
4.4 Cycle-Signature Mapper Structure of Multi-Dimensional 25
4.4.1 Row and Column 26
4.4.2 Diagonal 27
4.4.3 Reverse Diagonal 28
4.4.4 Pseudo-Random 29
4.5 Functional Validation 30
Chapter 5. Exploration of Multi- Dimensional Compaction-based Debugging Methodology 31
5.1 Metrics 32
5.1.1 Buggy Event Density (BED) 32
5.1.2 Bug Masking Probability (BMP) 32
5.1.3 Compression Ratio (CR) 33
5.1.4 Gate Count (GC) 33
5.2 Overview of the Exploration Tool 34
5.3 Exploration Flow of Exploration Tool 35
5.4 Automatically Generator 35
Chapter 6. Experimental Results 37
6.1 Exploration Setup 37
6.2 Exploration Results 38
6.2.1 Compression Ratio (CR) 38
6.2.2 Gate Count (GC) 39
6.2.3 Buggy Event Density (BED) 40
6.2.4 Bug Masking Probability (BMP) 41
6.3 Impact of Identification Precision on the Trace Buffer 42
Chapter 7. Conclusion and Future Work 43
References 44
Appendix A. Multi-Dimensional Signature Intersecting Degree 46
A.1 Introduction 46
A.2 Exploration Setup 47
A.3 Exploration Results 47

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