本論文採用TSMC 0.18m製程技術，在供應電壓1.8V之下，實作一個十位元，一千萬次取樣速率的雙模式類比數位轉換器。此電路將可應用於CMOS影像感測器中。
在電路設計上，類比數位轉換器的輸入源是從相關二次取樣或可程式化增益放大器的輸出決定，而且這兩種輸入都是已經經過取樣，因此有別於大部分的類比數位轉換器，不需要設計取樣保持電路。結合細調連續漸進式和粗調單斜率兩種模式，可產生邊緣圖像用於調整影像的清晰度。而在電容切換方面，利用7個周期來達到10位元的轉換，可有效降低功率消耗並提高轉換效率。因為輸入有兩種不同訊號可選擇，此電路也提供高解析度與低解析度兩種模式，在低解析度模式下，將沒有用到的電路短路，也可降低功率消耗。
本論文提出一個兩千萬次取樣速率的類比數位轉換器，在TSMC 0.18m製程下, 供應電壓為1.8 V, 取樣速率在10 MHz的情況下期望能達到INL及DNL小於 1, 功率消耗低於3mW的規格。

In this thesis, a 10-bit, 10 MS/s dual-mode analog-to-digital converter with a 1.8 V supply voltage is implemented by using the TSMC 0.18m process technology. This circuit primary is implemented for the CMOS Image Sensor.
In the circuit design, the input source of the analog-to-digital converter is determined by the output of the correlated double sampling or programmable gain amplifier, and both inputs are already sampled. Hence, it is different from the other analog digital converters. The sample and hold circuits can be not required in this cirucit. In combing with the fine step SAR and the coarse step single-slope modes, the edge images can be generated to adjust the sharpness of the image. By using 7 cycles in the capacitance switchig, the 10-bit conversion can effectively reduce the power consumption and increase the conversion efficiency. Because the input has two different signals to be chosen, this circuit also provides two modes of high resolution and low resolution. In the low resolution mode, the shortend and unused circuits also can reduce the power consumption.
In this thesis, a 10-bit, 10 MS/s analog-to-digital converter with a 1.8 V supply voltage is implemented by using the TSMC 0.18 m process technology. The INL and DNL need to be less than 1 and the power consumption should be less than 3mW.

論文審定書 i
中文摘要 ii
Abstract iii
目錄 iv
圖目錄 vi
表目錄 viii
Chapter 1. 緒論 1
1.1 研究動機與目標 1
1.2 論文組織 1
Chapter 2. 類比數位轉換器介紹 2
2.1 簡介 2
2.2 類比數位轉換器參數 2
2.2.1 最低有效位元(Least Significant Bit, LSB) 2
2.2.2 量化誤差(Quantization Error) 2
2.2.3 輸入訊號擺幅 3
2.2.4 靜態效能 4
2.3 類比數位轉換器架構簡介 8
2.3.1 單斜率類比數位轉換器(Single Slope ADC) 8
2.3.2 快閃式類比數位轉換器(Flash ADC) 9
2.3.3 管線式類比數位轉換器(Pipeline ADC) 10
2.3.4 連續逼近式類比數位轉換器(Successive Approximatiion ADC) 11
Chapter 3. 類比數位轉換器之設計考量 13
3.1 簡介 13
3.2 MOS開關 13
3.2.1 導通電阻(On Resistor) 13
3.2.2 電荷注入效應(Charge Injection) 15
3.2.3 時脈耦合效應(Clock Feedthrough) 17
3.2.4 導通電阻設計 17
Chapter 4. 目標架構介紹 19
4.1 CMOS類比數位轉換電路設計 19
4.2 目標架構 22
4.2.1 目標架構SAR ADC演算法 23
4.2.2 時脈產生器 26
4.2.3 模式切換判斷電路 28
4.2.4 具前級放大器的比較器 29
4.2.5 電容陣列數位類比轉換器邏輯控制電路 32
4.2.6 電容陣列 34
4.2.7 加法器電路 35
4.2.8 數位訊號同步輸出電路 36
4.3 類比數位轉換器之全電路佈局 37
Chapter 5. 效能與模擬結果 38
5.1 6位元SAR ADC效能與模擬結果 38
5.2 10位元SAR ADC效能與模擬結果 39
5.3 規格表比較 41
Chapter 6. 結論與未來研究方向 43
6.1 結論 43
6.2 未來展望 43
參考文獻 44

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