本論文採用TSMC 0.18μm 1P6M 1.8V 的混和訊號製程，設計出一個新式的主動式像素架構，有別於一般的線性型像素感測器(3T APS)和對數型像素感測器(Logarithmic Pixel)，分別在高低照度下有動態範圍不足的情形，本論文所提出的架構其動態範圍可高達160db，遠高於前述兩者架構，應用於高動態範圍的CMOS影像感測器。
電路設計方面，為了達到高動態範圍，本論採用線性-對數型主動式像素架構為基底進行改良，主要是將像素架構中的源極隨偶器輸出值回傳給此架構中對數型架構的電晶體閘極。當光電流較大時，源極隨偶器輸出值較低，藉此提高此電晶體的輸出電流，用以延遲光二極體感應端的電壓下降速率，提升像素感測器的動態範圍。此外此架構因電路複雜度較低，所以同時比一般高動態圍的感測器擁有較高的填充係數(Fill Factor)，可高達55%。

In this thesis, a new active pixel architecture is designed using TSMC 0.18μm 1P6M 1.8V mixed signal processing, which is different from linear pixel sensor (3T APS) and logarithmic pixel sensor (Logarithmic Pixel). There are cases where the dynamic range is insufficient under high and low illumination, respectively. The framework proposed in this thesis has a dynamic range of up to 160db, which is much higher than the above two architectures. It can be applied to the high dynamic range CMOS image sensors.
In terms of circuit design, in order to achieve high dynamic range, this thesis adopts a linear-logarithmic active pixel architecture as the base for improvement. The main purpose is to pass the output value of the source follower back to transistor’s gate, which is in the logarithmic architecture. When the photocurrent is large, the output value of the source follower is lower, thereby increasing the output current of the transistor to delay the voltage drop rate of the sensing terminal of the photodiode and improve the dynamic range of the pixel sensor. In addition, due to the low complexity of the circuit, this architecture also has a higher fill factor (Fill Factor), which can be as high as 55%, which is much better in the conventional high dynamic range sensors.

論文審定書 i
中文摘要 ii
Abstract iii
目錄 iv
圖目錄 vii
表目錄 ix
Chapter 1. 緒論 1
1.1 研究動機 1
1.2 論文架構組織 1
Chapter 2. 文獻回顧 2
2.1 影像感測器簡介 2
2.2 CCD和CMOS影像感測器 3
2.3 CMOS影像感測器感光流程 6
2.4 CMOS影像感測器感光原理 6
2.5 CMOS影像感測器特性參數介紹 8
2.6 CMOS影像感測器像素架構介紹 11
2.6.1. 被動式像素架構 12
2.6.2. 主動式像素架構 13
2.6.3. 數位式像素架構 15
Chapter 3. 電路設計 17
3.1 影像感測器系統架構簡介 17
3.2 像素架構 19
3.2.1. 線性-對數型像素架構 19
3.2.2. 電荷注入效應 20
3.2.3. 新式線性-對數型像素架構 21
3.3 相關取樣二次電路 24
3.4 Delta-Difference Sampling 26
3.5 解碼器 29
3.6 計數器 30
3.7 時脈產生器 32
3.8 偏壓電路 33
3.9 電路佈局 34
Chapter 4. 模擬結果 35
4.1 像素模擬 35
4.1.1. Iphoto current VS Vpixel readout 35
4.1.2. 動態範圍模擬結果 35
4.2 DDS電路模擬 38
4.3 解碼器模擬 41
4.4 計數器模擬 43
4.5 時脈產生器模擬 44
4.6 與其他文獻比較 45
4.6.1. 改良前的像素架構 VS 新式的像素架構 45
4.6.2. 與其它文獻比較(積分時間單位為us) 47
Chapter 5. 結論與未來展望 48
5.1 結論 48
5.2 未來展望 48
參考文獻 49

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