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博碩士論文 etd-0730104-151201 詳細資訊
Title page for etd-0730104-151201
論文名稱
Title
實現於ARM系統單晶片發展平台之視訊編解碼系統
Implementation of Video Codec System on ARM-based SoC Development Platform
系所名稱
Department
畢業學年期
Year, semester
語文別
Language
學位類別
Degree
頁數
Number of pages
64
研究生
Author
指導教授
Advisor
召集委員
Convenor
口試委員
Advisory Committee
口試日期
Date of Exam
2004-07-13
繳交日期
Date of Submission
2004-07-30
關鍵字
Keywords
ARM系統單晶片平台、軟體硬體共同設計、軟體硬體分割、離散小波轉換
HW/SW partitioning, HW/SW co-design, DWT, ARM-based SOC platform
統計
Statistics
本論文已被瀏覽 5638 次,被下載 26
The thesis/dissertation has been browsed 5638 times, has been downloaded 26 times.
中文摘要
近年來,由於晶片中可容納的電晶體數量愈來愈多,導致IC 設計的發展快速變化,傳統設計方法已不敷使用,而系統觀念的加入,更使得IC 設計變得複雜,所以近年來提倡利用軟/硬體共同設計的概念,搭配最新的製程技術,將系統逐漸整合於一顆單晶片中。本篇論文主要的目的是以軟體/硬體共同設計的概念,在系統層次上實際地去建構一個簡單視訊編解碼系統,並且透過ARM公司發展的SoC平台去實現它。由於是採取平台式的設計方法,我們所建立的軟體/硬體的模型都可在套用在ARM平台上未來相似的架構之中。

在我們的視訊編解碼系統上,其中一個部份就是使用離散小波轉換。近年來離散小波轉換已成功且廣泛地應用在許多不同的領域之中,並且由於與生俱來可階式的特性以及不錯的能量集中的特質,目前已經廣泛的被應用在各種影像編碼系統中。在硬體方面我們將實作使用5/3濾波器的上提式二維離散小波轉換,利用高階合成設計去建構出三種不同架構的上提式離散小波轉換,並且針對離散小波轉換的硬體使用率跟速度去改善,在考慮減輕軟體部份的處理和額外的記憶體存取次數之前提下,去克服在上提式離散小波轉換之中造成轉換不完美的邊界沿伸問題,再將設計完成的上提式離散小波轉換架構與RGB toYCbCr的硬體架構結合 在FPGA上去驗證它功能是否正確,然後再配合其他的軟體實現的部份,在ARM SOC平台上形成一個完整的視訊編碼系統。
Abstract
In the last years, with more and more transistors can fit into a chip, the growth the IC design complexity is fast and original design flow can’t cater for designers. Therefore, so many people promote to integrate the system into a single chip gradually with the last technology using the concept of hardware/software co-design. In this thesis, we use the hardware/software co-design concept to build a simple video codec from system level and implement it on the ARM’s SOC platform. We focus on the hardware/software co-ordination. Because we use the platform-based design method, the build hardware/software modules can be used in the similar architecture on the ARM platform
In our Video codec system, discrete wavelet transform(DWT) and RGBtoYCbCr are the most timing-consuming parts. Since DWT has inherent scalability and excellent features of energy compaction, it has been applied widely in the various image compression systems. We adopt the 5-3 filter lifting-based DWT in the hardware part of our system and design three different lifting-based DWT architectures by using the high level synthesis concept to optimize the hardware utilization and speed. In the premise of not increasing memory access times and additional processes of software, we overcome the boundary extension of DWT and verify it by means of FPGA after combining it with the RGBtoYCbCr hardware architecture. Finally, the hardware part is integrated with the other part implemented by software, we build a completely video encode system on the ARM SOC platform using the hardware/software co-design.
目次 Table of Contents
目次

第一章 緒論…..........................................................................................................1
1.1研究背景跟動機.................................................................................................1
1.2軟體/硬體共同設計...........................................................................................1
1.3章節概要.............................................................................................................4

第二章 視訊編碼演算法.......................................................................................5
2.1 前言.................................................................................................................5
2.2 WaveVideo演算法...........................................................................................5
2.3 色彩空間轉換.................................................................................................8

第三章 離散小波轉換..........................................................................................18
3.1 前言...............................................................................................................18
3.2 傳統式離散小波...........................................................................................18
3.3 二維離散小波轉換.......................................................................................20
3.4 上提式離散小波轉換...................................................................................26

第四章 上提式離散小波轉換設計..................................................................29
4.1 前言...............................................................................................................29
4.2 高階合成設計流程.......................................................................................29
4.3 一維架構延伸到二維架構...........................................................................38
4.4 總結.............................................................................................................. 44

第五章 軟體/硬體共同設計..............................................................................46
5.1 前言...............................................................................................................46
5.2 在ARM發展平台的設計流程.....................................................................46
5.3 軟體/硬體分割與排程.................................................................................50
5.4 實作結果.......................................................................................................54

第六章 結論............................................................................................................61
6.1總結................................................................................................................61
6.2未來方向.........................................................................................................61
參考文獻...................................................................................................................63
參考文獻 References
參考文獻
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[14] ARM INTERGRATOR/AP USER GUIDE
[15] ARM INTEGRATOR/CM920T-ETM INTEGRATOR/CM940T-ETM USER GUIDE
[16] ARM INTEGRATOR/LM-XCV600E+ INTEGRATOR/LM-EP20K600E+ USER GUIDE
[17] ARM MULTI-ICE version 2.2 USER GUIDE
[18]ARM DEVELOPER SUITE version 1.1 COMPILER, LINKER, AND UTILITIES GUIDE
[19] “AMBATM specification rev2.0”.
[20] ARM DEVELOPER SUITE version 1.1 CODEWARRIOR IDE GUIDE.
[21] ISO/IEC, ISO/IEC15444-1, Information technology – JPEG2000 image coding system, 2000.
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[23] Tan, K.-C.B.; Arslan, T, “Shift-accumulator ALU centric JPEG2000 5/3 lifting based discrete wavelet transform architecture”, Circuits and Systems, 2003. ISCAS '03 . Proceedings of the 2003 International Symposium, Volume: 5, 25-28 May 2003 Pages: V-161 - V-164 vol.5
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