MP3 音樂壓縮格式是現今一個非常重要的數位音響壓縮標準，由於具有極佳方便性以及優越性，使得它已經被廣泛的使用在多媒體的播放與儲存。在本論文中，我們採用軟、硬體共同設計的方法設計一個MP3播放系統。在設計的過程中我們引入了高階合成（High Level Synthesis）的設計觀念，此方法可有效的降低硬體所需要的成本並且有助於軟、硬體之間的排程，使其以較少的額外硬體成本達到即時播放的功能。
為了達到軟、硬體共同設計，我們將 MP3 解碼應用程式透過模擬分析找出運算中較規則且時間複雜度較高的部分，分別是逆改良型離散餘旋轉換（IMDCT）以及多相合成濾波器組（Poly Phase Synthesis Filter Bank）。然後將這兩部份以硬體實現，高階合成即用於幫助我們進行硬體部分最佳化以及軟、硬體間的整合，使得軟、硬體的溝通更為流暢。最後我們將所設計的低成本 MP3 解碼器在 SoC 的發展平台上進行軟、硬體共同驗證。
為了建構完整的驗證環境，我們在 SoC 發展平台中加入了簡單的輸入與輸出介面，其中輸入介面為網路卡，而輸出介面則包含音效卡以及網路卡。由於OS有助於軟、硬體之間的運作，所以我們在此發展平台上也建立一個以 Linux OS 為基礎的環境以管理所有的軟硬體資源，並且驅動相關的週邊硬體。

MP3 compression format is essential categorized one of the MPEG (Moving Picture Experts Group) standards for digital audio compression nowadays. For its superiority and convenient,MP3 has been widely used in multimedia player and storage application. In this thesis, we use software/hardware co-design methodology to design the MP3 player system. In addition, system level scheduling is adopted to arrange the execute time of SW and HW and significantly reduce the hardware cost under the construct of real-time processing. We can obtain fewer extra hardware cost while attaining the goal of real- time playing system. In order to perform software/hardware partitioning, simulate and analyze the MP3 application program to find out the critical parts with high time complexity and regular computation. These parts with high time complexity, e.g. IMDCT and Poly Phase synthesis filter bank, then are implemented by hardware to achieve better system performance. We use high level synthesis concept to optimize the hardware part and integrate software and hardware，such that communication between software and hardware can be performed smoothly. Finally, MP3 player system is using verified by hardware、software co- verified methodology on an SoC development platform.
In order to build a complete verification environment, we attach extra input and output interfaces to the SoC development platform, e.g. the network card and sound card. Write some driver to drive related peripheral device. Since OS is conducive to the operations between software and hardware, Linux OS is ported to the SoC platform to manage software and hardware resources and drive the peripheral devices.

Chapter 1 緒論…………………………………………………………………….1
1-1.研究動機…………………………………………………………..1
1-2 整體系統架構簡介..................................................................3
1-2.論文架構…………………………………………………………..3

Chapter 2 MP3 Decoder系統……………………………………………………6 2-1. MPEG Audio Layer III Decoding 簡介…………………………6
2-2. MP3 Decoder Theorem 解說…………………………………..7
2-2-1. MP3 Decoder 解碼流程…………………………………..7
2-2-2.同步化和CRC檢查…………………………………………8
2-2-3.旁資訊（Side information）............................................9
2-2-4. Scale Factor Selection Information（SCFSI）…………10
2-2-5. Side Information Format………………………………...10
2-2-6. Scale Factor Decoder…………………………………...11
2-2-7. 霍夫曼解碼……………………………………………….12
2-2-8. 逆量化(Invert Quantization)…………………………….13
2-2-9. Reorder…………………………………………………...14
2-2-10. Alias Reduction………………………………………....14
2-2-11. 立體聲效處理(Stereo Processing)…………………....15
2-2-12. IMDCT…………………………………………………...16
2-2-13. Poly Phase Synthesis Filter Bank…………………….18
2-3. MP3 Decoder 系統架構設計簡介…………………………….20
2-4. 軟、硬體分割（Software 、 Hardware Partition）…………20
2-5. 軟、硬體共同設計（Software 、 Hardware Co-Design）…21
Chapter 3 MP3 解碼器硬體實做………………………………………………23
3-1. MP3 Decoder 時間複雜度的分析…….………………...……23
3-2. IMDCT and Windowing分析………………………………….24
3-2-1. IMDCT and Windowing…………………………….……24
3-2-2. Arrangement……………………………………………...24
3-2-3. 演算法…….……………………………………………...25
3-3. 交錯式運算（interleave computation）………………………26
3-4. 改良交錯式演算法……………………………………………..27
3-5. IMDCT 硬體架構……………………………………………….28
3-5-1. 架構描述………………………………………………….28
3-5-2. 硬體架構排程…………………………………………....28
A. Multiplying - Add cumulating 高階合成排程…………28
B. Windowing 部分高階合成排程………………………..29
C. Overlap Adding 架構…………………………………...29
D. IMDCT 整體硬體架構…………………………………..30
3-6. Synthesis Filter Bank分析……………………………………...31
3-7. Synthesis Filter Bank演算法(Rule 3-6-2)…………………......33
3-8. Synthesis Filter Bank記憶體架構與對應………………………34
3-9. Synthesis Filter Bank演算法(Rule 3-6-1)……………………..36
3-10. Synthesis Filter Bank 硬體架構………………………………40
3-10-1. 架構描述………………………………………………..40
3-10-2. 硬體架構排程…………………………………………..40
A. COS係數 MA排程………………………………………..40
B. Dewindows係數 MA排程………………………………...41
C. Dew 和 Vbuff 負數運算處理………………………….....41
D. Synthesis Filter Bank 整體硬體架構…………………….42
3-11. MP3 Decoder內部運算方式…………………………………44
軟體前置處理方面.................................................................44
硬體方面...............................................................................45
飽和運算...............................................................................45
軟體後置處理方面.................................................................46

Chapter 4 系統排程………………………………………………………………48
4-1.系統排程…………………………………………………………48
A. 概念描述………………………………………………………48
B. 軟、硬體間的排程……………………………………………48
C. 軟體前後端處理與資料傳送時脈評估………………………49
D. 即時撥放時脈測量……………………………………………49
E. 記憶體最佳化…………………………………………………50
COS 係數……………………………………………………...50
Dewindow係數………………………………………………..50
Inverse quantization係數…………………………………….50
硬體暫存記憶體………………….……………………………50
軟體記憶體排程……………………………………………….51
排程解說...........……………………………………………….51
效能評估..........……………………………………….……….51
4-2. IMDCT系統排程………………………………………………..53
4-3. Synthesis Filter Bank系統排程……………………………….54
4-4. 效能提升..............................................................................54
Chapter 5 作業系統平台架構…………………………………………………...56
5-1.系統軟體架構………………………...………………………….56
5-2. 啟動載入器（Boot Loader）……………………………………56
A. 啟動監視器(Boot Monitor)…………………………………...56
B. Redboot……………………………………………………….56
C. Simple Loader with AFS (Arm Firmware Suit)…………….56
D. Cross Compilation…………………………………………...57
5-3. 核心………………………………………………………………58
5-4. Busy box…………………………………………………………59
5-5. 驅動程式………………………………………………………....59
5-6. 使用者程式………………………………………………………59
A. 使用者介面……………………………………………………59
B. MP3檔案要求………………………………………………...59

Chapter 6 介面的應用..........……………………………………………………61
6-1. 介面的整合……………………………………………………..61
6-2. 記憶體定址……………………………………………………..61
6-3. DMA實作內容…………………………………………………..62
6-4. DMA實作功能…………………………………………………..62

Chapter 7 相關的驗證..............………………………………………………...66
7-1. 功能和效能驗證的方法………………………………………..66
7-2. ASIC 的驗證方法......……………………………………….....68
7-3. ASIC 的驗證流程.................................................................68
7-4. 軟、硬體間的協調關係..........................................................68
7-5. ASIC 的合成結果.................................................................71
7-6. ASIC 的誤差率....................................................................73
Chapter 8 心得與結論..............………………………………………………..75
參考文獻 ..................................................................................................76

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[21]AMBATM specification rev2.0.

[22]ARM INTERGRATOR/AP USER GUIDE.

[23]ARM INTEGRATOR/CM920T-ETM INTEGRATOR/CM940T-ETM USER
GUIDE.

[24]ARM INTEGRATOR/LM-XCV600E+ INTEGRATOR/LM-EP20K600E+
USER GUIDE.

[25]ARM MULTI-ICE version 2.2 USER GUIDE.

[26]ARM DEVELOPER SUITE version 1.1 COMPILER,LINKER, AND
UTILITIES GUIDE.

[27]http://www.arm.com/

[28]http://www.altera.com/