Cu-Low k主要為低電阻值的材料與低介電係數的材料所構成之晶圓構造，主要是要減少因為路堆疊所造成之時間延遲效應使元件在速度方面的性能提高，並且可以降低功率的消耗(power dissipation)及雜訊干擾(cross-talk noise)。伴隨Cu/Low-K材料的使用，造成整個IC結構之機械 強度較差、熱膨脹係數較高，連帶的也衍生對IC封裝製程上的衝擊。
本論文主要是以實際生產作業情形針對Cu/Low-K引進所帶成對後段IC封裝的衝擊，針對品質有影響的製程，例如晶片切割時針對Cu/Low-K產品容易造成晶片剝裂之問題，銲線時針對Cu/Low-K 材料容易造成鋁墊剝裂，彈坑的問題，與封模後在Pre-condition測試及可靠度測試時針對Cu/Low-K 材料容易造成晶片Crack/Delamination 等問題用DOE/JMP 等驗證之方法，找出最佳化的作業條件，管控IC 在封裝製程的品質，進而達到品質的穩定使Cu/Low-K 材料可於進而大量生產

Copper interconnects and low k dielectrics have been introduced in advanced IC technology to reduce the interconnect resistance, improve the resistance to electromigration and reduce RC delay and cross talk effects. The introduction of new materials in integrated circuits makes the root cause determination and correction action implementation more challenging. Moreover, the complexity of package structure generates additional impact on degrading the yield of assembly processing manufacture.
This main purpose of this study is to investigate the influence of introducing Cu-/Low K wafer phase on actual manufacturing situation. Issues related to the failures of assembly process were analyzed for determining the root cause, in which such as die chipping issue during die sawing process, bond pad peeling/crater issues during wire bonding process and die crack / delamination issues after pre-condition and reliability test. The DOE/JMP methodology was used to achieve the optimium assembly processing condition so as to improve the quality of products, and then the mass production with stable yield could be realized.

第一章 緒論 …………………………………………………1
1-1 前言 …………………………………………………1
1-2 研究動機 ……………………………………………1
1-3 本文各章節之介紹 …………………………………7
第二章 理論基礎 ……………………………………………7
2-1 線路90nm 的介紹 …………………………………7
2-2 Low-K的介紹 ………………………………………7
2-2-1 Low-K 材料之選用 ………………………………..7
2-2-2 Low-K 材料之製造方法 …………………………..8
2-2-3 Low-K 材料之製造方法之比較 …………………..9
2-3 後段IC封裝製程得介紹 …………………………..10
2-3-1 上膠膜 (Wafer taping) ……………………………..11
2-3-2 晶片研磨 (Wafer grinding) ………………………..11
2-3-3 去膠膜 (Wafer detaping) …………………………..11
2-3-4 上膠膜 (Wafer mount) ……………………………..12
2-3-5 晶片切割 (Wafer sawing) ………………………….12
2-3-6 晶片黏著 (Die attach) ………………………………13
2-3-7 金線黏 (Wire bonding) ……………………………..13
2-3-8 封模站 (Molding Process) ………………………….14
2-3-9 去膠去鍏 (Dejunk /Trim) …………………………..14
2-3-10 穩定烘烤 (Post mold cure) ………………………..14
2-3-11 電鍍站 (Solder plating) ……………………………15
2-3-12 正印站 (Marking process) …………………………15
2-3-13 成形站 (Forming Singulation) …………………….15
2-3-14 包裝站 (Packing process) ………………………….15
2-4 Cu/Low-K 材料引進對後段IC封裝影響各站別得介紹 ……………………………………………………16
2-4-1 失敗模式介紹 ………………………………………17
第三章 實驗方法與步驟 ……………………………………21
3-1 晶圓切割製程參數的研究 …………………………21
3-1-1實驗流程 ……………………………………………21
3-1-2 實驗材料 …………………………………………...22
3-1-3 儀器設備 ……………………………………………22
3-1-4 實驗操作步驟 ………………………………………22
3-1-5 量測儀器 ……………………………………………23
3-1-6 量測儀器之原理 ……………………………………23
3-1-7 晶片Chipping 定義之規格 ………………………..24
3-2 晶圓切割製程切割刀種類的研究 ………………….25
3-2-1實驗流程 ……………………………………………..25
3-2-2 實驗材料 …………………………………………….26
3-2-3 儀器設備 …………………………………………….26
3-2-4 實驗操作步驟 ……………………………………….26
3-2-5 量測儀器 …………………………………………….26
3-2-6 量測儀器之原理 ……………………………………27
3-2-7 晶片Chipping 定義之規格 ………………………...27
3-3 銲線站最佳化參數之研究 …………………………..28
3-3-1實驗流程 …………………………………………….28
3-3-2 實驗材料 ……………………………………………29
3-3-3 儀器設備 ……………………………………………29
3-3-4 實驗操作步驟 ………………………………………29
3-3-5 量測儀器 ……………………………………………30
3-3-6 量測儀器之步驟 ……………………………………30
3-3-7 相關規格之定義 ……………………………………32
3-3-8 資料收集和分析方法 ………………………………34
3-4 封模站最佳化參數之研究 …………………………35
3-4-1實驗流程 ……………………………………………..35
3-4-2 實驗材料 …………………………………………….36
3-4-3 儀器設備 …………………………………………….39
3-4-4 實驗操作步驟 ……………………………………….39
3-4-5 量測儀器 …………………………………………….40
3-4-6 量測儀器之原理 …………………………………….40
3-4-7 可靠度實驗測試流程 ……………………………….41
3-4-8 可靠度實驗測試介紹 ……………………………….41
3-4-9 半導體封裝可靠度相關之故障機制 ………………43
3-4-10 相關規格之定義 …………………………………..46
第四章 結果與討論 ……………………………………….48
4-1 D/S process for CU/LOW-K 研究分析 ………48
4-2 W/B process for CU/LOW-K 研究分析 ……...50
4-3 M/D process for CU/LOW-K 研究分析 ………52
第五章 結論 ………………………………………………..55

[1] Numerical Study of Gold Wire Bonding Process on Cu/Low-K Structures; Viswanath A. G.K. ; Zhang X. ; Ganesh V. P. ; Chun L. ; Volume PP, Issue 99, 2007 Page(s):1 - 1
[2] Efficient Damage Sensitivity Analysis of advanced Cu/Low-K Bond Pad Structures Using Area Release Energy; van der Sluis, O.; Engelen, R.A.B.; van Driel, W.D.; van Gils, M.A.J.; van Silfhout, R.B.R.; 24-26 April 2006 Page(s):1 - 8
[3] Cu bonding to Cu low K wafers: a systematic study of the mechanical bonding process; Degryse, D.; Vandevelde, B.; Beyne, E.;18-20 April 2005 Page(s):41 - 48
[4] Interfacial adhesion of copper-low k interconnects; Andideh, E.; Scherban, T.; Sun, B.; Blaine, J.; Block, C.; Jin, B.; 4-6 June 2001 Page(s):257 – 259
[5] Integration and reliability of a manufacturable 130nm dual damascene Cu/Low-K process; bee, T.J.; Lim, Y.K.; Zhang, F.; Tan, D.; Siew, Y.K.; Perera, C.; Bu, X.M.; Chong, D.; Vigar, D.; Sun, S.C.; Volume 1, 18-21 Oct. 2004 Page(s):489 - 492 vol.1
[6] Optimization of Cu/Low-K bond pad designs to improve mechanical robustness using the Area Release Energy method; Engelen, R. A. B.; van der Sluis, O.; van Silfhout, R. B. R.; van Driel, W.D.; Fiori, V.; April 2007 Page(s):1 - 4
[7] Interfacial sliding and plasticity in back-end interconnect structures of microelectronic devices; Dutta, I.; Park, C.; Vella, J.; Pan, D.; 2004 Page(s):83 - 90
[8] Global (interconnect) warming; Banerjee, K.; Mehrotra, A.; Volume 17, Issue 5, Sept. 2001 Page(s):16 – 32
[9] Advanced HiCTE ceramic flip-Chipping of 90nm Cu/Low-K device: a novel material, package structure, and process optimization study; Chungpaiboonpatana, S.; Shi, F.G.; 31 May-3 June 2005 Page(s):1491 - 1496 Vol. 2
[10] 300mm low k wafer dicing saw study; Wang ZhiJie; Wang, S.; Wang, J.H.; Lee, S.; Yao Su Ying; Han, R.; Su, Y.Q.; 30 Aug.-2 Sept. 2005 Page(s):262 – 268
[11] Wire bonding process impact on Cu/Low-K Dielectric material in damascene copper integrated circuits;Kripesh, V.; Sivakumar, M.; Loon Aik Lim; Kumar, R.; Iyer, M.K.; 28-31 May 2002 Page(s):873 – 880
[12] Direct Non-Contact Electrical Measurement of Cu/Low-K Damage in Patterned Cu/Low-K Films by a Near-Field Scanned Microwave Probe; Tsai, J.S.; Hsu, J.W.; Shieh, J.H.; Jang, S.M.; Liang, M.S.; 2006 Page(s):112 – 113
[13] Process challenges in Cu/Low-K wafer dicing; Hanxie Zhao; Dianne Shi; 16-18 July 2003 Page(s):401 – 407
[14] Packaging effects on reliability of Cu/Low-K interconnects; Guotao Wang; Merrill, C.; Jie-Hua Zhao; Groothuis, S.K.; Ho, P.S.; Volume 3, Issue 4, Dec. 2003 Page(s):119 – 128
[15] Low damage via formation with low resistance by NH3 thermal reduction for Cu/ultra Cu/Low-K interconnects;Okamura, H.; Ogawa, S.; 7-9 June 2004 Page(s):42 – 44
[16] Packaging effect on reliability for Cu/low k structures; Guotao Wang; Groothuis, S.; Ho, P.S.; 25-29 April 2004 Page(s):557 – 562
[17] Resist stripping process development for porous Cu/Low-K Dielectric materials;
Han Xu; Jacobs, T.; White, B.; Josh Wolf, P.; 31 March-1 April 2003 Page(s):142 - 147