本論文第一部分主要探討8位元微控器軟體開發環境實作之方法，包含Compiler、Assembler、Debugging mechanism等四大部分。其中Debugging mechanism的設計以電路擬真器(ICE)為基礎。
電路擬真器(ICE)是微處理器常見的除錯技術，在論文中所設計之ICE包括硬體實作和搭配除錯使用的軟體。 ICE硬體主要是IEEE 1149.1 std. TAP Controller組成之控制電路，控制著串連在data bus上的scan cell；除錯軟體透過IEEE 1149.1 std. JTAG port從PC端輸入除錯指令給ICE硬體。
本論文第二部分針對ICE(in-circuit emulator)硬體電路整合軟體端除錯器的過程，提出自行設計版本與商業套裝除錯軟體支援兩種方式。實作範例除了整合實驗室32bit微處理器與ICE硬體外，對於控制ICE電路之軟體除錯器之驗證，將以可程式邏輯電路-FPGA證明兩種整合方法皆可行。

In this thesis, the first section will talk about how to implement the software development environment for 8bit microprocessor, including Compiler, Assembler, and Debugging mechanism etc. The design of Debugging mechanism is based on in-circuit emulator.
In-circuit emulator is a common debugging technique for microprocessor. The designed ICE contains hardware implement and debugging software for it in this thesis. ICE hardware is a control circuit from TAP Controller, IEEE 1149.1 std. and it control the scan cells on the data bus. The Debugging software uses JTAG port, IEEE 1149.1 std., to insert debug instruction from PC to ICE hardware.
In this thesis, the second section will focus on the process of integrating ICE hardware circuit and software debugger issued by two ways, our own design version and business suit debugging software support. The examples are not only integrating our LAB’s 32bit microprocessor and ICE hardware, but also verifying software debugger to control ICE circuit by FPGA to prove above two methods are work.

Chapter 1 . 論文簡介 1
1.1研究背景 1
1.2 研究動機 3
1.3 研究方法 3
1.4 主要貢獻 3
1.5 論文大綱 4
Chapter 2 相關研究 5
2.1 常見的整合型程式開發環境工具 5
2.2 組譯器 8
2.3 指令集模擬器(ISS) 9
2.4 軟體除錯器 10
Chapter 3 . 八位元微控器軟體開發環境設計之概念 13
3.1 八位元微控器之組譯器開發 13
3.2 八位元微控器之指令集模擬器開發 16
3.3 八位元微控器之除錯器開發 17
Chapter 4 . SYS8MI微控器之軟體開發環境 22
4.1 SYS8MI微控器軟體開發環境介紹 22
4.2 SYS8MI微控器之組譯器設計 24
4.3 SYS8MI微控器之指令集模擬器設計 28
4.4 軟硬體協同驗證功能支援 34
4.5 SYS8MI微控器之JTAG介面軟體除錯器設計 38
Chapter 5 . 實作驗證 52
5.1 SYS8MI微控器 應用程式開發範例說明 54
泡沫排序法、Fanbonacci數列 – 常見數學運算函式 54
5.2 SYS8MI微控器 設計驗證平台說明 57
Chapter 6 . 結論與展望 58
附錄一. 實作範例 : 32位元微處理器與電路擬真器整合 59
1.1 JTAG介面之電路擬真器(ICE)硬體架構介紹 59
1.2 32位元微處理器之電路擬真器硬體架構與功能 60
1.3 對應32位元微處理器之電路擬真器之軟體除錯器設計 64
1.4 FPGA驗證 80
附錄二. Example : How to modify the ICE to support a commercial debug tool 85
1. Introduction 85
1.1 Motivation 85
1.2 Implementation flow 85
1.3 The Difference between our Developed 32bit Microprocessor’s ICE Debugging Tool and Commercial Debug Tool Support 87
2. Background 100
2.1 ARM ICE hardware (ARM7TDMI) 100
2.2 ARM RealView Debugger 101
2.3 Multi-ICE protocol Converter 102
3. The function analysis of RealView Debugger 105
3.1 Target detection 105
3.2 Free-Run 111
3.3 External Stop 112
3.4 CPU Registers 113
3.5 Memory 114
3.6 Breakpoint / Watchpoint 116
3.7 Single Step 121
3.8 Load Image 124
4. Integration Environment for the 32bit microprocessor’s ICE and the commercial debug tool 126
4.1 Prototyping Board SetUp 126
4.2 Connection between prototyping board and the commercial debug tool 132
4.2.1 JTAG Interface Connection 133
4.2.2 Reset Circuit 134
4.2.3 Connection Troubleshooting 135
4.2.4 Using Logic Analyzer 139
4.2.5 RTL Simulation Model 141
5. Modification of the 32bit microprocessor’s ICE for the commercial debug tool 146
5.1 CPU 146
5.2 ICE 150
6. Verification Plan and Results 163
6.1 Verification Flow 163
6.1.1 Coding style checking 163
6.1.2 Code coverage 165
6.2 Experiment of FPGA 32bit microprocessor’s ICE for a commercial debug tool 165
7. Conclusion 177
8. IP Deliverables 178
參考文獻 (References) 179

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