論文使用權限 Thesis access permission:校內校外完全公開 unrestricted
開放時間 Available:
校內 Campus: 已公開 available
校外 Off-campus: 已公開 available
論文名稱 Title |
渦輪碼解碼器之最大後驗機率演算法之電路設計 Circuit Design of Maximum a Posteriori Algorithm for Turbo Code Decoder |
||
系所名稱 Department |
|||
畢業學年期 Year, semester |
語文別 Language |
||
學位類別 Degree |
頁數 Number of pages |
52 |
|
研究生 Author |
|||
指導教授 Advisor |
|||
召集委員 Convenor |
|||
口試委員 Advisory Committee |
|||
口試日期 Date of Exam |
2010-07-08 |
繳交日期 Date of Submission |
2010-07-30 |
關鍵字 Keywords |
最大後驗機率演算法、渦輪碼 Maximum a Posteriori Algorithm, Turbo code |
||
統計 Statistics |
本論文已被瀏覽 5707 次,被下載 1730 次 The thesis/dissertation has been browsed 5707 times, has been downloaded 1730 times. |
中文摘要 |
渦輪碼解碼器的電路設計對現今通訊系統,如第三代行動通訊是相當重要的研究課題。在渦輪碼解碼器的架構中用來儲存分支路徑值與狀態路徑值的記憶體,不論是在功率消耗與面積上都占了整體架構的絕大部份。因此在本論文中是以編碼端暫存器交換(register exchange)與追蹤前置(trace forward)的方法,透過排列記憶體讀取順序來有效管理記憶體的使用量,進而達到降低記憶體使用面積之目的。 軟體模擬是用Matlab模擬在通道為加成性白高斯雜訊 (Additive White Gaussian Noise,AWGN) 下,以二位元相位偏移 (Binary Phase Shift Keying, BPSK) 調變傳輸資料,在渦輪碼解碼器解碼之後觀察其位元錯誤率 (Bits Error Rate,BER),因資料序列通常為一連串隨機連續序列,適當地切割再傳輸可以有效降低記憶體使用量,故分析資料序列經過切割再傳輸與未切割直接傳輸兩者的差異,藉由調整切割長度使得差異性到達合理可接受範圍。 |
Abstract |
none |
目次 Table of Contents |
第一章 緒論............................................................................................................ 1 1.1 研究背景與動機………………………………………………………...1 1.2 各章提要………………………………………………………………...2 第二章 渦輪碼原理與架構.................................................................................... 3 2.1 渦輪碼原理……………………………………………………………...3 2.2 渦輪編碼器架構………………………………………………………...4 2.3 內部交織器架構………………………………………………………...7 2.4 渦輪解碼器架構……………………………………………………….10 2.4.1 最大事後機率演算法……………………………………………..11 a 2.4.2 對數化最大事後機率演算法………………………...…………...14 2.5 可移動式視窗架構…………………………………………………….16 第三章 渦輪碼解碼器電路設計.......................................................................... 19 3.1 分支路徑運算單元…………………………………………………….20 3.2 加法比較選擇差值運算單元………………………………………….21 3.3 對數化概似比值運算單元…………………………………………….25 3.4 追蹤前置演算法……………………………………………………….26 第四章 系統模擬.................................................................................................. 34 4.1 Matlab Simulation……………………………………………………...34 第五章 結論………………………………………….………………………….41 參考文獻...................................................................................................................... 42 |
參考文獻 References |
[1] C. Berrou and A. Glavieux and P. Thitimajshima, “Near Shannon limit error-correcting coding and decoding: turbo codes,” in Proc. ICC ‘93, pp. 1064-1070, May 1993. [2] C. Berrou and A. Glavieux, “Near optimum error correcting coding and decoding: turbo-codes ,” IEEE Trans. Communication, Vol. 44, pp.1261-1271, Oct. 1996. [3] “3rd Generation Partnership Project; Technical Specification Group Radio Access Network; Multiplexing and channel coding(FDD) (Release 7),” 3GPP TS 25.212 v7.4.0, Mar. 2007. [4] L. R. Bahl, J. Coke, F. Jelink, and J. Raviv, “Optimal decoding of linear codes for minimizing symbol error rate,” IEEE Trans. Inform. Theory, Vol. 42, pp. 429-455, Mar. 1974. [5] P. Robertson, E. Villebrn, and P. Hoeher, “A comparison of optimal and sub-optimal MAP decoding algorithms operating in the domain,” in Proc. ICC’95, pp. 1009-1013, June 1995. [6] Forney, G. D., Jr., Concatenated Codes, Cambridge, Massachusetts: M. I. T. Press, 1966. [7] J. H. Yuen, et. al., “Modulation and Coding for Satellite and Space Communications,” in Proc. IEEE, vol. 78, no. 7, July 1990, pp. 1250-1265. [8] J. Hagenauer and P. Hoeher, “A Viterbi algorithm with soft-decision outputs and its applications,” in Proc. IEEE Global Telecommunications Conference 1989, Dallas, Texas, Nov. 1989, pp. 1680-1686. [9] J. A. Erfanian and S. Pasupathy, “Low-complexity parallel-structure symbol by symbol detection for ISI channels,” in Proc. IEEE Pacific Rim Conf. on Commu.,Computers and Signal Processing, pp. 350-353, June, 1989. [10] A. J. Viterbi, “An intuitive justification and a simplified implementation of the MAP decoder for convolutional codes,” IEEE J. Select. Areas in Commu., vol. 16, pp. 260-264, Feb., 1998. [11] C. Bai, J. Jiang, and P. Zhang, “Simplified recursive structure for turbo decoder with Log-MAP algorithm,” IEEE 55th Conf., vol. 2, pp. 1012-1015, May, 2002. [12] P. J. Black and T. H. Meng, “A 140-Mb/s, 32-state, radix-4, Viterbi decoder,” IEEE J. Solid-State Circuits, vol. 27, no. 12, pp. 1877–1885, Dec. 1992. [13] E. Boutillon, W. J. Gross, and P. G. Gulak, “VLSI architectures for the MAP algorithm,” IEEE Trans. on Commu., vol. 51, No. 2, Feb., 2003. |
電子全文 Fulltext |
本電子全文僅授權使用者為學術研究之目的,進行個人非營利性質之檢索、閱讀、列印。請遵守中華民國著作權法之相關規定,切勿任意重製、散佈、改作、轉貼、播送,以免觸法。 論文使用權限 Thesis access permission:校內校外完全公開 unrestricted 開放時間 Available: 校內 Campus: 已公開 available 校外 Off-campus: 已公開 available |
紙本論文 Printed copies |
紙本論文的公開資訊在102學年度以後相對較為完整。如果需要查詢101學年度以前的紙本論文公開資訊,請聯繫圖資處紙本論文服務櫃台。如有不便之處敬請見諒。 開放時間 available 已公開 available |
QR Code |