渦輪碼解碼器的電路設計對現今通訊系統，如第三代行動通訊是相當重要的研究課題。在渦輪碼解碼器的架構中用來儲存分支路徑值與狀態路徑值的記憶體，不論是在功率消耗與面積上都占了整體架構的絕大部份。因此在本論文中是以編碼端暫存器交換(register exchange)與追蹤前置(trace forward)的方法，透過排列記憶體讀取順序來有效管理記憶體的使用量，進而達到降低記憶體使用面積之目的。
軟體模擬是用Matlab模擬在通道為加成性白高斯雜訊 (Additive White Gaussian Noise，AWGN) 下，以二位元相位偏移 (Binary Phase Shift Keying, BPSK) 調變傳輸資料，在渦輪碼解碼器解碼之後觀察其位元錯誤率 (Bits Error Rate，BER)，因資料序列通常為一連串隨機連續序列，適當地切割再傳輸可以有效降低記憶體使用量，故分析資料序列經過切割再傳輸與未切割直接傳輸兩者的差異，藉由調整切割長度使得差異性到達合理可接受範圍。

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第一章 緒論............................................................................................................ 1
1.1 研究背景與動機………………………………………………………...1
1.2 各章提要………………………………………………………………...2
第二章 渦輪碼原理與架構.................................................................................... 3
2.1 渦輪碼原理……………………………………………………………...3
2.2 渦輪編碼器架構………………………………………………………...4
2.3 內部交織器架構………………………………………………………...7
2.4 渦輪解碼器架構……………………………………………………….10
2.4.1 最大事後機率演算法……………………………………………..11 a
2.4.2 對數化最大事後機率演算法………………………...…………...14
2.5 可移動式視窗架構…………………………………………………….16
第三章 渦輪碼解碼器電路設計.......................................................................... 19
3.1 分支路徑運算單元…………………………………………………….20
3.2 加法比較選擇差值運算單元………………………………………….21
3.3 對數化概似比值運算單元…………………………………………….25
3.4 追蹤前置演算法……………………………………………………….26
第四章 系統模擬.................................................................................................. 34
4.1 Matlab Simulation……………………………………………………...34
第五章 結論………………………………………….………………………….41
參考文獻...................................................................................................................... 42

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