在本篇論中，我們提出一個3D折疊式非傳統單載子互補金氧半場效電晶體(3D fold-up non-classical Unipolar CMOS-FET)結構與原理。我們使用一個有貫穿效應(punch through effect)的NMOS電晶體和一個傳統NMOS電晶體構成的邏輯閘，來實現互補金氧半場效電晶體(CMOS)操作。我們提出的CMOS電路，其驅動和負載部分都是由NMOS電晶體所構成，所以傳輸的帶電載子只會有高速的電子，因此延遲時間比傳統CMOS改善了14%。此外結構不需要使用到PMOS電晶體作為負載與驅動電晶體，所以不需要使用到N型井的技術，而我們又採用3D方式的結構，因此總體的面積比傳統CMOS改善了69%，若元件運用在大型積體電路(VLSI)上，則可以大幅提高電路的積集密度(packing density)，而成本上也可以獲得降低。因此我們提出3D折疊式非傳統單載子互補金氧半場效電晶體在面積、速度、成本將會有很大的獲利。

In this thesis, we propose a three-dimensional (3D) fold-up non-classical unipolar complementary metal-oxide semiconductor field-effect transistor (CMOS-FET) structure and its operation mechanism. We utilize a NMOS transistor having punch-through effect and a classical NMOS to realize our proposed CMOS circuit. In our proposed CMOS circuit, both driver and load transistors are based on the n-channel MOS (NMOS) structures, so, in this unipolar CMOS, the carrier used is the electron only. Hence, the delay time can be improved by 14% when compared with the conventional CMOS. Moreover, the p-channel MOS (PMOS) transistor can be eliminated in our proposed CMOS circuit. Thus, we do not need the traditional N-well technique and we also use the 3D device architecture to drastically reduce the total device area more than 69%, in comparison to a conventional CMOS. If our proposed CMOS architecture is implemented in the VLSI circuits, the packing density can be increased and the device fabrication cost can also be reduced significantly. Therefore, our proposed 3D fold-up non-classical single-carrier CMOS-FET can achieve three important requirements as follows: 1) area reduction, 2) enhanced speed, and 3) decrease cost in the system fabrication.

第一章 導論 1
1.1 背景 1
1.2 動機 2
第二章 原理與元件操作說明 19
2.1 原理說明與物理模型應用 19
2.1.1 貫穿效應 (Punch Through Effect) 19
2.1.2 空間電荷寬度 (Space Charge Width) 20
2.1.3 閘極控制空乏層厚度 22
2.1.4 平帶電壓 (Flat-Band Voltage) 23
2.1.5 功函數 (Work Function) 24
2.1.6 臨界電壓 (Threshold Voltage) 25
2.1.7 傳統互補式金氧半場效電晶體基本操作原理 26
2.2 3D折疊式非傳統單載子互補金氧半電晶體操作原理 29
2.2.1 負載線 32
第三章 原件設計與製程 38
3.1 3D折疊式非傳統單載子互補金氧半元件模擬設計 38
3.1.1 3D折疊式非傳統單載子互補金氧半場效電晶體 38
3.1.2 元件模擬設計 39
第四章 結果與討論 42
4.1 元件製程模擬結果與物理模型應用 42
4.1.1 單一式模型結果比較與討論 43
4.1.2 混合式模型(Mixed-Mode)結果比較與討論 57
4.2 延遲時間 64
4.3 3D折疊式非傳統單載子CMOS與傳統CMOS佈局比較 65
4.4 邏輯電路的應用 67
第五章 總結論 79
參考文獻 80
附錄A 84

[1] S.-M Kang and Y. Lwblebigi 著 黃正光, 吳紹懋 譯“CMOS digital integrated circuits analysis and desidn,” 全華科技圖書股份有限公司 第二版.
[2] T. Hiramoto, “Transistor evolution for CMOS extension and future information processing technologies,” IEEE Int. Workshop on Junction Technology, June 2009, pp. 3-6.
[3] C.-H. Chen, T.-L. Lee, T.-H. Hou, C.-L. Chen, C.-C. Chen, J.-W. Hsu, K.-L. Cheng, Y.-H.Chiu, H.-J. Tao, Y. Jin, C.-H. Diaz, S.-C. Chen, and M.-S. Liang, “Stress memorization technique (SMT) by selectively strained-nitride capping for sub-65nm high-performance strained-si device application,” in VLSI Symp. Tech. Dig., June 2004, pp. 56-57.
[4] C. Ortolland1, P. Morin, C. Chaton, E. Mastromatteo, C. Populaire, S. Orain, F. Leverd,P. Stolk, F. Boeuf and F. Arnaud “Stress memorization technique (SMT) optimization for 45nm CMOS,” in VLSI Symp. Tech. Dig., March 2006, pp. 78-79.
[5] K.-M. Tan, M. Yang, W.-W. Fang, A. E.-J. Lim, R. T.-P. Lee, T.-Y. Liow, and Y. -C. Yeo “Performance benefits of diamond-like carbon liner stressor in strained p-channel field-effect transistors with silicon–germanium source and drain,” IEEE Electron Device Lett., vol. 30, no. 3, pp. 250-253, March 2009.
[6] T.-Y. Liow, K.-M. Tan, R. T. P. Lee, M. Zhu, K.-M. Hoe, G. S. Samudra, N. Balasubramanian, and Y.-C. Yeo “Spacer removal technique for boosting strain in n-channel FinFETs with silicon-carbon source and drain stressors,” IEEE Electron Device Lett., vol. 29, no. 1, pp. 80-82, January 2008.
[7] M. Miyamoto, N. Sugii, Y. Hoshino, Y. Yoshida, M. Kondo, Y. Kimura, and K. Ohnishi “Thick-strained-Si/SiGe CMOS technology with selective-epitaxial-Si shallow-trench isolation,” IEEE Trans. Electron Device, vol. 54, no. 9, pp. 2460-2465, Sep. 2007.
[8] 林宏年, 呂嘉裕, 林鴻志, 黃調元, “局部與全面形變矽通道(strained Si channel)互補式金氧半(CMOS) 之材料、製程與元件特性分析(II),國家奈米實驗室_奈米通訊期刊, 第十二卷, 第二期, pp.18-22.
[9] C. Ortolland, Y. Okuno, P. Verheyen, C. Kerner, C. Stapelmann, M. Aoulaiche, N. Horiguchi, and T. Hoffmann, “Stress memorization technique—fundamental understanding and low-cost integration for advanced CMOS technology using a nonselective process,” IEEE Trans. Electron Device, vol. 56, no. 8, pp. 1690-1697, August 2009.
[10] G. Hellings, J. Mitard, G. Eneman, B. D. Jaeger, D. P. Brunco, D. Shamiryan, T. Vandeweyer, M. Meuris, M. M. Heyns, and K. D. Meyer, “High performance 70-nm germanium pMOSFETs with boron LDD implants,” IEEE Electron Device Lett., vol. 30, no. 1, pp. 88-90, January 2009.
[11] G. Nicholas, B. D. Jaeger, D. P. Brunco, P. Zimmerman, G. Eneman, K. Martens, M. Meuris, and M. M. Heyns, “High-performance deep submicron Ge pMOSFETs with halo implants,” IEEE Trans. Electron Device, vol. 54, no. 9, pp. 2503-2511, Sep. 2007.
[12] N. Patil, A. Lin, E. R. Myers, H.-S. P Wong, and S. Mitra, “Integrated wafer-scale growth and transfer of directional carbon nanotubes and misaligned-carbon-nanotube-immune logic structures,” in VLSI Symp. Tech. Dig., 2008, pp. 205-206.
[13] G. T. Goeloe, E. W. Mabyt, D. J. Silversmith, R. W. Mountain and D. A. Antoniadist, “Vertical single-gate CMOS inverters on laser-processed multilayer substrates,” IEDM Tech. Dig., 1981, pp. 554-556.
[14] S. KAWAMURA, N. SASAKI, T. IWAI, M. NAKANO, M. TAKAGI, “Three-dimensioal CMOS IC’s fabricated by using beam recrystallization,” IEEE Electron Device Lett., vol. 4, no. 10, pp. 366-368, Oct. 1983.
[15] G. Roos and B. Hoefflinger, “Complex 3D CMOS circuits based on a triple-decker cell,” IEEE J. Solid-State Circuits, Vol. 27, NO. 7, pp. 1067-1072, July 1992.
[16] G. Roos, B. Heffiinger, M. Schubert, and R. Zingg, “High-density ASICs with A three-dimensional CMOS process,” VLSI Technology,Systems, and Applications, 1991, pp. 297-300.
[17] S.-H. Song, K.-R. Kim, S. Kang, J.-H. Kim, J.-I. Huh, K.-C. Kang, K.-W. Song, J.-D. Lee, and B.-G. Park,“Analytical modeling of field-induced interband tunneling-effect transistors and its application,” IEEE Trans. Nanotechnol., vol. 5, no. 3, pp. 192-200, May 2006.
[18] K.-R. Kim, H.-H. Kim, K.-W. Song, J.-I. Huh, J.-D. Lee, and B.-G. Park,“Field-induced interband tunneling effect transistor (FITET) with negative-differential transconductance and negative-differential conductance,” IEEE Trans. Nanotechnol., vol. 4, no. 3, pp. 317-321, May 2005.
[19] K. J. Kuhn, ”CMOS scaling beyond 32nm: challenges and opportunities,” IEEE Design automation conf., 2009, pp. 310-313.
[20] M. Haselman, and S. Hauck, ”The Future of Integrated Circuits: A Survey of Nanoelectronics,” IEEE Proceedings, vol. 98, no1, Jan 2010, pp. 11-38.
[21] T. P. Ma, “Proposes Unipolar CMOS,”Semiconductor International, Oct. 8, 2008.
[22] J.-W. Han, S.-W. Ryu, S.-J. Choi, and Y.-K. Choi, ”Gate-induced drain-leakage (GIDL) programming method for soft-programming-free operation in unified RAM (URAM),” IEEE Electron Device Lett., vol. 30, no. 2, pp. 189-191, Feb. 2009.
[23] 施敏, 伍國珏 著 張鼎張, 劉柏村 譯 “半導體元件物理,” 國立交通大學 第三版.
[24] D. A. Neamen 著 楊賜麟 譯 “半導體物理與元件,” 滄海書局.
[25] B. G. Streetmane and S. K. Banerjee 著 吳孟奇, 洪勝富, 連振炘, 龔正, 吳忠義 譯“半導體元件,” 東華書局.
[26] 施敏 著 黃調元 譯 “半導體元件物理與製作技術,” 國立交通大學 第二版.
[27] B. M. Wilamowski, R. C. Jaeger, ”The Lateral Punch-Through Transistor,” IEEE Electron Device Lett., vol. 3, no. 10, pp. 277-280, Oct. 1982.
[28] F.-C. Hsu, R. S. Muller, C. Hu; P.-K. Ko, ”A Simple Punchthrough Model for Short-Channel MOSFET‘s,” IEEE Trans. Electron Device, vol. 30, no. 10, pp. 1354-1359, Oct. 1983.