在本論文中，我們提出一個僅以電子為傳輸載子的單極性金氧半場效電晶體(Unipolar CMOS)，因為皆為由NMOS構成，故稱Unipolar CMOS。而且我們利用模擬方式成功得到好的反向器的輸出以及邏輯電路的應用。透過新的機制，利用崩潰電流來取代傳統PMOS的操作電流做為充電電流，能夠改善tPLH，使得我們的元件在平均延遲時間(tp)上比傳統CMOS減少23%，而且此電流在操作上是非破壞性的，並不影響元件。而我們所提出之Unipolar CMOS，因為皆為NMOS而免去了製作N或P井區的製程，且可忽略載子移動率的不同而省去尺寸上的設計，另外擁有共用電極的優點，讓Unipolar CMOS在光罩佈局上比起傳統CMOS可省去75%的面積，進而提升電路上的密集度。

In this paper, we propose a novel Unipolar CMOS device in which the transport carriers are electron only. And we achieve good inverter output waveform and logic circuit applications by simulation. Duo to all n-channel (NMOS) structures are used, we call this proposed CMOS as a Unipolar CMOS. A new basic theory of utilizing the punch through effect is
demonstrated to enhance the tPLH in our proposed Unipolar CMOS. The average delay time compared with the classical CMOS circuit can be improved 23% for high-performance applications. For our proposed Unipolar CMOS, all n-channel MOS are used to eliminate the N- and P-well processes and ignore the difference between the carrier mobility. In addition, the common electrodes are also exploited, hence, the layout area can be reduced to about 75%, which leads to significantly increase the packing density of CMOS circuits in the same chip.

第一章 導論 1
1.1 背景 1
1.2 動機 2
第二章 元件運用機制與操作原理 12
2.1 運用機制 12
2.2 操作原理 13
2.2.1 貫穿效應(Punch Through Effect) 13
2.2.2 空乏區的計算 13
2.2.3 內嵌氧化物之NMOS空乏區分布以及其操作 15
2.3 傳統CMOS 16
2.3.1 傳統CMOS連接方式 16
2.3.2 Conventional CMOS之負載線與轉移特性曲線 17
2.4 Unipolar CMOS 19
2.4.1 元件工作時輸出入之各端點電壓狀況 19
2.4.2 Unipolar CMOS之負載線與轉移特性曲線 22
第三章 元件結構設計與製造 26
3.1 元件設計 26
3.1.1 平帶電壓(Flat-Band Voltage) 26
3.1.2 臨限電壓(Threshold Voltage) 27
3.2 實際製造流程 28
3.3 模擬考量要點 31
第四章 模擬結果之電性討論 32
4.1 模擬考慮之物理模型說明與參數設定 32
4.1.1 物理模型說明 32
4.2 電性分析與討論 33
4.2.1內嵌氧化物之Unipolar CMOS 34
4.2.2 Conventional CMOS 44
4.3 基本邏輯電路模擬 50
4.3.1 NOR GATE 50
4.3.2 NAND GATE 52
4.3.3 靜態隨機存取記憶體(SRAM)電路之latch模擬 53
4.4 其他(利用GIDL電流) 56
第五章 結論與未來展望 59
5.1 結論 59
5.2 未來展望 59
參考文獻 60
附錄
A. 個人著作及全文
B. 共同著作

[1] International Technology Roadmap for Semiconductor (ITRS) (2009).
[2] 施敏, 伍國珏 著 張鼎張, 劉柏村 譯, “半導體元件物理學 第三版,” 國立
交通大學出版社。
[3] K.-J. Chui, K.-W. Ang, N. Balasubramanian, M.-F. Li, G. S. Sanudra, and Y.-C.
Yeo, “n-MOSFET With Silicon-Carbon Source/Drain for Enhancement of
Carrier Transport,” IEEE Trans. Electron Device, vol. 54, no. 2, pp. 249-256, Feb.
2007.
[4] Y.-C. Lin, H Yamaguchi, E.-Y. Chang, Y.-C. Hsieh, M. Ueki, Y. Hirayama, C.-Y.
Chang, “Growth of very-high-mobility AlGaSb/InAs high-electron-mobility
transistor structure on si substrate for high speed electronic applications,”
Applied Physics Lett., vol. 90, no. 2, pp. 023509 – 023509-3, 2007.
[5] B. R Bennett, B. P. Timkham, J. B. Boss, M. D. Lange, and R. Tsai, “Materials
growth for InAs high electron mobility transistors and circuits,” J. Vac. Sci.
Technol. B, vol. 22, no. 2, pp. 688-694, 2004.
[6] R. J. P. Lander, Y. V. Ponomarev, J. G. M. van Berkum, and W. B. de Boer,
“High Hole Motilities in Fully-Strained Si1-xGex Layers (0.3<x<0.4) and their
significance for SiGe pMOSFET Performance,” IEEE Trans. Electron Device,
vol. 48, no. 8, pp. 1826-1832, Aug. 2001.
[7] L. Washington, F. Nouri, S. Thirupapuliyur, G. Eneman, P. Verheyen, V. Moroz,
L. Smith, X. Xu, M. Kawaguchi, T. Huang, K. Ahmed, M. Balseanu, L.-Q. Xia,
M. Shen, Y. Kim, R. Rooyackers, K. De Meyer and R. Schreutelkamp,
“pMOSFET With 200% Mobility Enhancement Induced by Multiple Stressors,”
IEEE Electron Device Lett. , vol. 27, no. 6, pp. 511-513, June 2006.
62
[8] H.-W. Chen, C.-H. Ko, T.-J. Wang, C.-H. Ge, Kehuey Wu, and W.-C. Lee,
“Enhanced Performance of Strained CMOSFETs Using Metallized Source/Drain
Extension (M-SDE),” in VLSI Technology Symposium, 2007, pp. 118-119.
[9] W.-C. Lee, B. Watson, T.-J. King, and C. Hu, “Enhancement of PMOS Device
Performance with Poly-SiGe Gate,” IEEE Electron Device Lett. , vol. 20, no. 5,
pp. 232-234, May 1999.
[10] W. C. Yeh, R. C. Jaeger, and K. B. Cook, “A New CMOS Structure with
Vertical p-Channel Transistors,” IEEE Electron Device Lett. , vol. 4, no. 6, pp.
196-198, June 1983.
[11] K.-C. Liu, S.K. Ray, S.K. Oswal, N.B. Chakraborti, R.D. Chang, D.L. Kencke,
and S.K. Banerjee, “Enhancement of Drain Current in Vertical SiGe/Si PMOS
Transistors Using Novel CMOS Technology,” in Device Research Conf., 1997,
pp. 128-129.
[12] D. A. Neamen 著 楊賜麟 譯, “半導體物理與元件,” 滄海書局。
[13] T.-P. Ma, Semiconductor International, 10/8/2008.
[14] T. Nakamura, M. Yamamoto, H. Ishikawa, and M. Shinoda, “Submicron
Channel MOSFET's Logic Under Punchthrough,” IEEE Journal of Solid-State
Circuits vol. 13, no. 5, pp. 572-577, 1978.
[15] V. Nathan and N. C. Das, “Gate-Induced Drain Leakage Current in MOS
Devices,” IEEE Trans. Electron Device, vol. 40, no. 10, pp. 1888-1890, Oct.
1993.
[16] X. Yuan, J.-E. Park, J. Wang, E. Zhao, D. C. Ahlgren, T. Hook, J. Yuan, V. W.
C. Chan, H. Shang, C.-H. Liang, R. Lindsay, S. Park, and H. Choo,
“Gate-Induced-Drain-Leakage Current in 45-nm CMOS Technology,” IEEE
Trans. Device and Materials Reliability, vol. 8, no. 3, pp. 501-508, Sep 2008.
[17] A. Chaudhry and M. J. Kumar, ”Controlling Short-Channel Effects in
63
Deep-Submicron SOI MOSFETs for Improved Reliability,” IEEE Trans. Device
and Materials Reliability, vol. 4 no. 1, pp. 99-109, Mar 2004.
[18] S. Veeraraghavan and J. G. Fossum, ”Short-Channel Effects in SOI MOSFETs,”
IEEE Trans. Electron Device, vol. 36, no. 3, pp. 522-528, Mar 1989.
[19] J.-P. Coling, ”Silicon-On-Isolator Technology：Materals to VLSI, ”Kluwer
Academic Publishers, pp. 107-208.
[20] A S. Sedra and K. C. Smith, “Microelectronic Circuits fifth editon,” Oxford
University press.
[21] F.-C. Hsu, R. S. Muller, C. Hu and P.-K. Ko, “A Simple Punchthrough Model for
Short-Channel MOSFET's,” IEEE Trans. Electron Device, vol. 34, no. 10, pp.
1354-1359, Aug. 1983.
[22] User’s Manual, ISE-TCAD, 2004.
[23] S.-M. Kang and Y. Leblebigi 著 黃光正, 吳紹懋 譯, “CMOS 數位積體電路
分析與設計,” 全華科技圖書股份有限公司。