Responsive image
博碩士論文 etd-0731106-103712 詳細資訊
Title page for etd-0731106-103712
論文名稱
Title
含優質本體縛點之下閘極薄膜電晶體之製作與模擬
Fabrication and Simulation of the Bottom Gate Thin Film Transistor with Smart Body Tie
系所名稱
Department
畢業學年期
Year, semester
語文別
Language
學位類別
Degree
頁數
Number of pages
79
研究生
Author
指導教授
Advisor
召集委員
Convenor
口試委員
Advisory Committee
口試日期
Date of Exam
2006-07-14
繳交日期
Date of Submission
2006-07-31
關鍵字
Keywords
下閘極、自體加熱效應、扭結效應、薄膜電晶體
Bottom Gate, Self Heating Effect, Kink Effect, TFT
統計
Statistics
本論文已被瀏覽 5706 次,被下載 9152
The thesis/dissertation has been browsed 5706 times, has been downloaded 9152 times.
中文摘要
在本論文中,我們製作出一種含優質本體縛點(body tie)之TFT元件。傳統的TFT元件在製程上通常使用浪費太大面積之本體縛點,且元件本身也因埋藏層 (buried oxide)熱傳導係數不佳而有嚴重的自體加熱效應(self-heating effect),這些不理想之因素將導致元件可靠度(reliability)及ICs的集積度 (packing density)下降;因此我們提出類似薄膜電晶體(TFT)底部閘極(bottom gate)的架構,來達成優質本體縛點;不但源、汲極能自動升起且有助於3D立體製程技術的發展;同時為了抑制短通道效應及降低漏電流,我們挖除大部分之PN接面面積,形成超薄型薄膜(ultra-thin film)的本體;此外,我們在底部閘極兩旁形成適當厚度的邊襯(spacer)讓源、汲極不靠得太近,可減少米勒電容效應(Miller's capacitance effect)。
根據ISE TCAD 9.5模擬發現,含優質本體縛點之SOI元件,能紓緩載子在通道中所衍生出來的〝自體加熱效應〞及有效消除因撞擊游離 (impact ionization)在輸出特性曲所造成的扭結(kink)現象,提高元件崩潰電壓與可靠度。雖然趨動電流因寄生電阻而略降,但在飽和區之輸出曲線卻是平滑的;而元件之短通道效應也因挖除過多之PN接面面積,形成超薄型薄膜的本體而被抑制,使得元件性能提升。
Abstract
In this thesis, a bottom gate TFT with smart body tie device is realized, For a PDSOI devices, which usually uses large layout areas of body ties, and it has self-heating effect resulting from the buried oxide between the silicon film and substrate, which has a lower thermal conductivity.
In order to suppress the short channel effect and reduce leakage current, we dug out in advance the PN junction to formed the ultra thin film body, besides, in order to reduce Miller's capacitance effect we formed enough thickness of spacer at both sides of the bottom gate and let the source and the drain region do not too closer nearly.
According to the simulation results of ISE TCAD, the TFT with smart body tie device can alleviate self-heating effect and can achieve kink-free at output characteristic curve due to hot carriers by impact ionization and enhance the breakdown voltage of the device. Although the drive current of the TFT device lower than conventional TFT due to the parasitic resistance in the body region, the output characteristic curve is smooth in the saturation zone; the device suppress the short channel effect and improve the performance of the device due to most areas of PN junction are dug out.
目次 Table of Contents
第一章 導論 1
第二章 新元件結構模擬 5
2-1 四種結構 (bulk_BG、SBT、UTB、UTBSBT) 輸入特
性曲線模擬 5
2-2 短通道效應整理 (short channel effect) 10
2-3 浮體效應 (floating body effect) 13
2-4 自體加熱效應 (self heating effect) 19
2-5 模擬結論 26

第三章 新元件結構的設計與製作 27
3-1 標準第零層製作 28
3-2 成長burried oxied與定義閘極 30
3-3 沉積閘極氧化層 32
3-4 定義主動區域 33
3-5 形成源、汲極區域 34
3-6 形成ultra-thin body 34
3-7 定義contact hole區域形成smart body tie 35
3-8 金屬連線 36
第四章 實作結果與討論 38
4.1 IDS - VGS 特性曲線 38
4.2 IDS - VDS特性曲線 39
4.3 實作元件 cross section SEM 45
4.4 結論 47
第五章 結論與未來發展 48
Reference 49
附錄 A : Layout 圖 54
B : 本篇論文獲得中華民國專利 55
C: 投稿的會議論文 56
參考文獻 References
[1]S. Veeraraghavan and J.G.Fossum, “ Short Channel Effects in SOI MOSFET’s” , IEEE Trans. Electron, Vol. 36, P.522, 1989.
[2]H. B. Bakoglu, “Circuits Interconnections and Packaging for VLSI”, Addison Wesley Publishing Company, Singapore, P.38 - P.40, 1990.
[3]Jean-Pieere Coling, “Silicon-On-Isolator Technology: Materials to VLSI,” Kluwer Academic Publishers, P.107 - P.108
[4]G. C. Messenger and M. S Ash, “The Effects of Radiation Electronic System,” Van Nostrand Reinhold Company, New York, P.307, 1986.
[5]A. J. Auberton-Herve, “Proceedings of the fourth international Symposium on Silicon-On-Insulator Technology and Device”, Ed. By D.N. Schmidt, Vol. 90 - 6, P.544, 1990.
[6]R. R. Troutman, “Latchup in CMOS Technology”, Kluwer Academic Publishers, P.54 – P.56, 1986.
[7]Chenming Hu, “SOI and Device Scaling,” Proceedings 1998 IEEE International SOI Conference, P.18 – P.22, Oct. 1998.
[8]S. Christoloveanu, and G. Reichert, “Recent Advances in SOI Materials and Device Technologies for High Temperature,” IEEE Trans. Electron Devices, P.86 - P.93, 1998.
[9]Dallmann, D.A.; Shenai, K.; Electron Devices, “Scaling Constraints Imposed by Self-Heating in Submicron SOI MOSFET”, IEEE Transactions on Vol 42, P.489 - P.496, March. 1995.
[10]L. T. Su, J. E. Chung, D. A. Antoniadis, K. E. Goodson, and M. I. Filk, “Measurement and modeling of self-heating in SOI MOSFET’s,” IEEE Trans. Electron Devices, Vol. ED-41, P.698 - P.675, Jan. 1994.
[11]Y. Apanovich, E. Lyumkis, B. Polsky and P. Blakey, “Non-isothermal analysis of breakdown in soi transistors,” IEEE Trans. Electron Devices, Vol. ED-40, P. 2094 - P.2096, Nov. 1993.
[12]Roig, J.; Flores, D.; Vellvehi, M.; Rebollo, J.; Millan, J.; “Novel Techniques for Reducing Self-Heating Effects in Silicon On Insulator Power Devices,” Semiconductor Conference, 2001. CAS 2001 Proceedings. International, Vol. 2, P.493 – P.496, Oct. 2001
[13]Cole, B.; Parke, S.; “A Methode to Overcome Self-Heating Effects in SOI MOSFETs” University/Government/Industry Microelectronics Symposium, P.295 - P.297, July. 2003
[14]羅正中 張鼎張 譯 “半導體製程技術導論” 學銘圖書有限公司 P.353 - P.355, 2003.
[15]Sivaram, P.; Anand, B.; Desai, M.P.; “Silicon Film Thickness Considerations in SOI-DTMOS,” Electron Device Letters, IEEE Vol. 23, Issue 5, P.276 - P.278, May. 2002.
[16]Hongchin Lin; Lin, J.; Chang, R.C.; “Inversion-Layer Induced Body Current in SOI MOSFETs With Body Contact,” Electron Device Letters, IEEE Vol. 24, Issue 2, P.111 - P.113, Feb. 2003
[17]Pemmaraju, S.; Parke, S.A.; “Elimination of body effects in SOI CMOS devices,” Microelectronics and Electron Devices, 2004 IEEE Workshop on 2004 P.126 - P.128
[18]Busta, H.H.; Pogemiller, J.E.; Standley, R.W.; Mackenzie, K.D.; “Self-aligned bottom-gate submicrometer-channel-length a-Si-:H thin-film transistors,” Electron Devices, IEEE Transactions on Vol 36, Issue 12, P.2883 - P.2888, Dec. 1989.
[19]Shimizu, K.; Sugiura, O.; Matsumura, M.; “High-performance bottom-gate poly-Si/SiN TFTs on glass-substrate,” Electron Devices Meeting, 1992. Technical Digest. P.669 - P.672, Dec. 1992.
[20]Kwon-Young Choi; Kee-Chan Park; Cheol-Min Park; Min-Koo Han; “A new bottom-gated poly-Si thin-film transistor,” Electron Device Letters, IEEE Vol 20, Issue 4, P.170 - P.172 , April. 1999.
[21]Shengdong Zhan; Ruqi Han; Chan, M.J.; “A novel self-aligned bottom gate poly-Si TFT with in-situ LDD” Electron Device Letters, IEEE Vol 22, Issue 8, P.393 - P.395, Aug. 2001.
[22]H. C. Lin, C. Y. Lu, M.F. Wang, and T. Y. Huang“Ambipolar Schottky Barrier SOI MOSFETs” Semiconductor Device Research Symposium, 2001 International, 5 - 7 Dec. 2001.
[23]Colinge, J.-P.; “Reduction of kink effect in thin-film SOI MOSFETs,” Electron Device Letters, IEEE Vol 9, Issue 2, P.97 - P.99, Feb. 1988.
[24]Ying-Che Tseng; Huang, W.M.; Diaz, D.C.; Ford, J.M.; Woo, J.C.S.; “AC floating-body effects in submicron fully depleted (FD) SOI nMOSFETs and the impact on analog applications,” Electron Device Letters, IEEE Vol 19, Issue 9, P.351 - P.353, Sept. 1998.
[25]Marshall, A.; Natarajan, S.; “PD-SOI and FD-SOI: a comparison of circuit performance,” Electronics, Circuits and Systems, 2002. 9th International Conference on Vol 1, P.25 - P.28, Sept. 2002.
[26]Zhikuan Zhang; Shengdong Zhang; Mansun Chan; “Self-align recessed source drain ultrathin body SOI MOSFETZ,” Electron Device Letters, IEEE Vol. 25, Issue 11, P.740 - P.742, Nov. 2004.
[27]Tsu-Jae King; “Taking silicon to the limit: challenges and opportunities”Solid-State and Integrated Circuits Technology, 2004. Proceedings. 7th International Conference on Vol. 1, P.1 - P.5, Oct. 2004.
[28]J. P. Colinge, “Reduction pf kink effect Thin-Film SOI MOSFET,” IEEE Electron Device Letters, Vol. 19, P.97 - P.99, June. 1988.
[29]Valdinoci, M.; Colalongo, L.; Baccarani, G.; Fortunato, G.; Pecora, A.; Policicchio, I.; “Floating body effects in polysilicon thin-film transistors” IEEE Electron Device Letters, Vol. 44, P.2234 - P.2241, June. 1997.
[30]Makoto Yoshimi., etc., “Suppression of the floating-body effect in SOI MOSFET's by the bandgap engineering method using a Si1-xGex source structure” IEEE Trans. Electron Devices, Vol. 44, March. 1997.
[31]Vincent M. C., etc., “,” IEEE Trans. Electron Devices, Vol. 44, July. 1997.
[32]P. S. Jue, J. T. Lin, “Study and Simulation on a New SOI Device with High Transconductance,” Master thesis, NSYSU, Taiwan, P.9 - P.33, 1998.
[33]Y. Y. Hsu, J. T. Lin, “The Study on characteristics of a 3-wide SOI MOSFET,” Master thesis, NSYSU, Taiwan, P.28 – P.33, 1999.
[34]F. Balestra, S. Cristoloveanu, M. Benachir, J. Brini, and T. Elewa, “Double-gate silicon-on-insulator transistor with volume inversion: A new device with greatly enhance performance,” IEEE Electron Device Letters, Vol. 8, P.410 - P.12, 1987.
[35]S. Matsuda, T. Sato, H. Yoshimura, “Novel Corner Rounding Process for Shallow Trench Isolation utilizing MSTS (Micro-Structure Transformation of Silicon),” IEDM, P.137 - P.140, 1998.
[36]Jeffrey Sleight, Kaizad Mistry, “A Compact Schottky Body Contact Technology for SOI Transistors,” IEDM, P.419 - P.422, 1997.
[37]Jeffrey Sleight, Kaizad Mistry, “DC and Transient Characterization of a Compact Schottky Body Contact Technology for SOI Transistors,” IEEE Transacitions on Electron Device, Vol. 46, P.1451 - P.1456, July. 1999.
[38]Kunihiro Suzuki, Tetsu Tanaka, Yoshiharu, Hiroshi Horie, and Yoshihiro Arimoto, “Scaling Theory for Double-Gate SOI MOSFET’s,” IEEE Transacitions on Electron Device, Vol. 40, P.2329 - P.2329, Dec. 1993.
[39]Bogdan Majkusiak, Tomasz Janik, and Jakub Walczak, “Semiconductor Thickness Effects in the Double-Gate SOI MOSFET,” IEEE Transacitions on Electron Device. Vol. 45, P.1127 - P.1134, May. 1998.
[40]Emil Arnold, “Double-Charge-Sheet Model for Thin Silicon-on-Insulator Films,” IEEE Transacitions on Electron Devices. Vol. 43, P.2153 – P.2163, Dec. 1996.
[41]A. Vandooren, S. Cristoloveanu, and J. P. Colinge, “Hall Mobility Measurement in Double-Gate SOI MOSFET,” IEEE International SOI Conference, P.118 - P.119, Oct. 2000.
[42]Jean-Pieere Coling, M. H. Gao, A. Romano-Rodríguez, “SILICON-ON-INSULATOR “GATE-ALL-AROUND DEVICE,” IEDM, P.595 - P.598, 1995.
[43]J. P. Colinge, X. Baie, and V. Bayot, “Evidence of Two-Dimensional Carrier Confinement in Thin n-Channel SOI Gate-All-Around (GAA) Device,” IEEE Electron Device Letters, Vol. 15, P.193 - P.195, June. 1994.
[44]Victor. W. C. Chan and Philip C. H. Chan, “Fabrication of Gate-All-Around Transistors Using Metal Induced Lateral Crystallization,” IEEE Electron Device Letters, Vol. 22, P.80 - P.82, Feb. 2001.
[45]Digh Hisamoto, Toru Kaga, Yoshifumi Kawamoto and Eiji Takeda, “Impact of the Vertical SOI “DELTA” Structure on Planar Device Technology,” IEEE Transacitions on Electron Device, Vol. 38, P.1419 - P.1424, June. 1991.
[46]H. Wang, M. Chan, “The Behavior of Narrow-width SOI MOSFET’s with MESA Isolation,” IEEE Transacitions on Electron Devices. Vol. 47, P.593 - P.600, March. 2000.
[47]Samuel K. H. Fung, “Impact of Scaling Silicon Film Thickness and Channel Width on SOI MOSFET with Reoxidized MESA Isolation,” IEEE Transacitions on Electron Devices. Vol. 45, P.1105 - P.1110, May. 1998.
[48]B. Davari, R. H. Dennard, and G. G. Shahidi, “CMOS Scaling for High Performance and Low Power-The Next Ten Years,” IEEE Proc., Vol. 83, P.595 - P.606, Apr. 1995.
[49]Mike S. L. Lee, Bernard M. Tenbroek, “A Physically Based Compact Model of Partially Depleted SOI MOSFET for Analog Circuit Simulation,” IEEE Journal of Solid-State Circuit, Vol. 36, P.110 - P.121, Jan. 2001.
[50]Jongoh Kim, Taewoo Kim, Jaebrom Park, Woojin Kim, Byungseop Hong, and Gyuhan Yoon, “A shollow Trench Isolation Using Nitric Oxide (NO)-Annealed Wall Oxide to Suppress Inverse Narrow Width Effect,” IEEE Electron Device Letters, Vol. 21, P.575 - P.577, Dec. 2000.
[51]J. B. Kuo, Y. G. Chen, “Sidewall-Related Narrow Channel Effect in Mesa-Isolated Fully-Depleted Ultra-Thin SOI NMOS Device,” IEEE Electron Device Letters, Vol. 16, P.379 - P.381, Sep. 1995.
[52]Samuel K. H. Fung, Mansun Chan, and Ping K. Ko, “Impact of Scaling Silicon Film Thickness and Channel Width on SOI MOSFET with Reoxidized MESA Isolation,” IEEE Transacitions on Electron Devices, Vol. 45, P.1105 - P.1110, May. 1998.
[53]Bhavna Agrawal, Vivek K. De, and James. D. Meindl, “Three-Dimensional Analytical Subthreshold Models for Bulk MOSFET’s,” IEEE Transacitions on Electron Devices, Vol. 42, P.2170 - P.2180, May. 1995.
[54]Kelvin Kuey-Lung Hsueh, Julian J. Sanchez, Thomas A. Demassa, and Lex A. Akers, “Inverse-Narrow-Width Effects and Small-Geometry MOSFET Threshold Voltage Model,” IEEE Transacitions on Electron Devices, Vol. 35, P.325 - P.338, March. 1988.
[55]Chun-Yen Chang, Sun-Jay Chang, Tien-Sheng Chao, Sung-Dtr Wu, and Tiao-Yuan Huang, “Reduced Reverse Narrow Channel Effect in Thin SOI nMOSFETs,” IEEE Electron Dvice Letters, Vol. 21, P.460 - P.462, Sep. 2000.
[56]Mishel Matloublan, Ravishankar Sundaresan, and Hsindao Lu, “Measurement and Modeling of the Sidewall Threshold Voltage of Mesa-Isolated SOI MOSFET’s,” IEEE Transacitions on Electron Devices, Vol. 36, P.938 - P.942, May. 1989.
[57]Steve Shao-Shiun Chung, and Tung-Chi Li, “An Analytical Threshold-Voltage Model of Trench-Isolated MOS Device with Nonuniformly Doped Substrates,” IEEE Transacitions on Electron Devices, Vol. 39, P.614 - P.622, Mar. 1992.
[58]Donald A. Neamen, “Semiconductor Physics and Device, 2nd ed.” IRWIN, P.504 - P.507, 1999.
電子全文 Fulltext
本電子全文僅授權使用者為學術研究之目的,進行個人非營利性質之檢索、閱讀、列印。請遵守中華民國著作權法之相關規定,切勿任意重製、散佈、改作、轉貼、播送,以免觸法。
論文使用權限 Thesis access permission:校內外都一年後公開 withheld
開放時間 Available:
校內 Campus: 已公開 available
校外 Off-campus: 已公開 available


紙本論文 Printed copies
紙本論文的公開資訊在102學年度以後相對較為完整。如果需要查詢101學年度以前的紙本論文公開資訊,請聯繫圖資處紙本論文服務櫃台。如有不便之處敬請見諒。
開放時間 available 已公開 available

QR Code