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博碩士論文 etd-0731106-164424 詳細資訊
Title page for etd-0731106-164424
論文名稱
Title
一新能克服自我加熱效應及浮體效應的多晶矽薄膜電晶體製作方法
A novel Poly-Si TFT process method for overcoming Self-heating effect and Floating body effect
系所名稱
Department
畢業學年期
Year, semester
語文別
Language
學位類別
Degree
頁數
Number of pages
61
研究生
Author
指導教授
Advisor
召集委員
Convenor
口試委員
Advisory Committee
口試日期
Date of Exam
2006-07-14
繳交日期
Date of Submission
2006-07-31
關鍵字
Keywords
多晶矽薄膜電晶體、自我加熱效應、浮體效應
floating body effect, Poly-Si TFT, self-heating effect
統計
Statistics
本論文已被瀏覽 5664 次,被下載 5142
The thesis/dissertation has been browsed 5664 times, has been downloaded 5142 times.
中文摘要
在本論文中,我們提出一新能克服自我加熱效應及浮體效應的多晶矽薄膜電晶體製作方法。傳統多晶矽薄膜電晶體主要缺點就是有自我加熱效應及浮體效應的存在。自我加熱效應會導致汲極電流的下降,而浮體效應會導致元件的提早崩潰及扭結效應。在此我們利用各種不同的絕緣技術形成不連續性的深埋氧化層,在不連續深埋氧化層之間有pass ways,它們將主動區與基底直接連接。因為傳統的LOCOS絕緣技術會有較長之鳥嘴,SILO及PBL絕緣技術的類似方法被使用來降低鳥嘴。在此,我們也使用STI的絕緣技術形成不連續性的深埋氧化層,此法較易於控制pass way的寬度。經由量測可以證明pass way成功地減緩自我加熱效應及浮體效應。
Abstract
In this thesis, we present a new Poly - Si TFT process method to overcome Self - heating effect and Floating body effect. The main drawback of a conventional Poly - Si TFT is the existence of self - heating effect and floating body effect. The self - heating effect leads to drain current reduced and the floating body effect leads to premature device breakdown and kink effects. Here, we utilize all kinds of different isolation technologies to form non - continuing buried layer. Between the non - continuing buried layer there are pass ways, which contact the active region and the substrate directly. Because of conventional LOCOS isolation technology has longer bird’s beak, the familiar method of SILO and PBL isolation technologies are used to reduce bird’s beak. Also, we use STI isolation technology to build up non - continuing buried layer, which can control the width of pass way more easily. It is proved from
the measurement that the pass way can slow down the self - heating effect and the floating body effect successfully.
目次 Table of Contents
第一章 緒論 1

第二章 模擬結果與討論 7
2.1 部份空乏之新元件與傳統SOI MOSFET的模擬與比較 7
2.1.1 IDs - VDs 特性曲線之探討 8
2.1.2 IDs - VGs 特性曲線之探討 11
2.2 完全空乏之新元件與傳統SOI MOSFET的模擬與比較 13
2.2.1 IDs - VDs 特性曲線之探討 15
2.2.2 IDs - VGs 特性曲線之探討 16
2.3 結論 19

第三章 元件設計與製作 20
3.1 製作零層 20
3.2 製作SILO oxide層 22
3.3 元件隔離及完成主動區域 29
3.4 沉積Gate Oxide及完成閘極區域 33
3.5 形成源極與汲極區域 37
3.6 製作Contact Hole 38
3.7 製作金屬層 39

第四章 實驗結果量測與討論 41
4.1 半導體元件參數量測說明與注意事項 41
4.2 IDs - VGs 特性曲線之探討 42
4.3 IDs - VDs 特性曲線之探討 44
4.4 結論 45

第五章 結論 46

參考文獻 47
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